From: Richard Henderson <richard.henderson@linaro.org>
Date: Mon, 23 Mar 2020 17:22:30 +0000 (+0000)
Subject: target/arm: Assert immh != 0 in disas_simd_shift_imm
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=3944d58db3fc5bf131345a21a44013bc13849a12;p=qmiga%2Fqemu.git

target/arm: Assert immh != 0 in disas_simd_shift_imm

Coverity raised a shed-load of errors cascading from inferring
that clz32(immh) might yield 32, from immh might be 0.

While immh cannot be 0 from encoding, it is not obvious even to
a human how we've checked that: via the filtering provided by
data_proc_simd[].

Reported-by: Coverity (CID 1421923, and more)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200320160622.8040-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 8fffb52203..032478614c 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10405,6 +10405,9 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
     bool is_u = extract32(insn, 29, 1);
     bool is_q = extract32(insn, 30, 1);
 
+    /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
+    assert(immh != 0);
+
     switch (opcode) {
     case 0x08: /* SRI */
         if (!is_u) {