From: Simon Tatham <simon.tatham@arm.com>
Date: Thu, 27 Jun 2019 12:41:12 +0000 (+0000)
Subject: [ARM] Fix bogus assertions in copyPhysReg v8.1-M cases.
X-Git-Tag: android-x86-9.0-r1~1230
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=3a2501e0a008bddedac40894a0b160b315e86495;p=android-x86%2Fexternal-llvm.git

[ARM] Fix bogus assertions in copyPhysReg v8.1-M cases.

The code to generate register move instructions in and out of VPR and
FPSCR_NZCV had assertions checking that the other register involved
was a GPR _pair_, instead of a single GPR as it should have been.

Reviewers: miyuki, ostannard

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63865

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364534 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index de8a04632f5..222aa85856a 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -927,25 +927,25 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
     return;
   } else if (DestReg == ARM::VPR) {
-    assert(ARM::GPRPairRegClass.contains(SrcReg));
+    assert(ARM::GPRRegClass.contains(SrcReg));
     BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_P0), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc))
         .add(predOps(ARMCC::AL));
     return;
   } else if (SrcReg == ARM::VPR) {
-    assert(ARM::GPRPairRegClass.contains(DestReg));
+    assert(ARM::GPRRegClass.contains(DestReg));
     BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_P0), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc))
         .add(predOps(ARMCC::AL));
     return;
   } else if (DestReg == ARM::FPSCR_NZCV) {
-    assert(ARM::GPRPairRegClass.contains(SrcReg));
+    assert(ARM::GPRRegClass.contains(SrcReg));
     BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_FPSCR_NZCVQC), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc))
         .add(predOps(ARMCC::AL));
     return;
   } else if (SrcReg == ARM::FPSCR_NZCV) {
-    assert(ARM::GPRPairRegClass.contains(DestReg));
+    assert(ARM::GPRRegClass.contains(DestReg));
     BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_FPSCR_NZCVQC), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc))
         .add(predOps(ARMCC::AL));