From: Matt Arsenault Date: Mon, 16 May 2016 20:58:23 +0000 (+0000) Subject: SelectionDAG: Select min/max when both are used X-Git-Tag: android-x86-7.1-r4~33367 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=3b880e33a0c61ed2500d4883b139e00eac1a0988;p=android-x86%2Fexternal-llvm.git SelectionDAG: Select min/max when both are used Allow two users of the condition if the other user is also a min/max select. i.e. %c = icmp slt i32 %x, %y %min = select i1 %c, i32 %x, i32 %y %max = select i1 %c, i32 %y, i32 %x git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269699 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 58751b785e4..aa39c7874ac 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -2697,6 +2697,14 @@ void SelectionDAGBuilder::visitFCmp(const User &I) { setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition)); } +// Check if the condition of the select has one use or two users that are both +// selects with the same condition. +bool hasOnlySelectUsers(const Value *Cond) { + return std::all_of(Cond->user_begin(), Cond->user_end(), [](const Value *V) { + return isa(V); + }); +} + void SelectionDAGBuilder::visitSelect(const User &I) { SmallVector ValueVTs; ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(), @@ -2782,7 +2790,7 @@ void SelectionDAGBuilder::visitSelect(const User &I) { // If the underlying comparison instruction is used by any other // instruction, the consumed instructions won't be destroyed, so it is // not profitable to convert to a min/max. - cast(&I)->getCondition()->hasOneUse()) { + hasOnlySelectUsers(cast(I).getCondition())) { OpCode = Opc; LHSVal = getValue(LHS); RHSVal = getValue(RHS); diff --git a/test/CodeGen/AMDGPU/select-i1.ll b/test/CodeGen/AMDGPU/select-i1.ll index 6735394e93a..2406831b94c 100644 --- a/test/CodeGen/AMDGPU/select-i1.ll +++ b/test/CodeGen/AMDGPU/select-i1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; FIXME: This should go in existing select.ll test, except the current testcase there is broken on SI @@ -13,3 +13,15 @@ define void @select_i1(i1 addrspace(1)* %out, i32 %cond, i1 %a, i1 %b) nounwind ret void } +; FUNC-LABEL: {{^}}s_minmax_i1: +; SI-DAG: buffer_load_ubyte [[COND:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:44 +; SI-DAG: buffer_load_ubyte [[A:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:45 +; SI-DAG: buffer_load_ubyte [[B:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:46 +; SI: v_cmp_eq_i32_e32 vcc, 1, [[COND]] +; SI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]] +define void @s_minmax_i1(i1 addrspace(1)* %out, i1 zeroext %cond, i1 zeroext %a, i1 zeroext %b) nounwind { + %cmp = icmp slt i1 %cond, false + %sel = select i1 %cmp, i1 %a, i1 %b + store i1 %sel, i1 addrspace(1)* %out, align 4 + ret void +} diff --git a/test/CodeGen/AMDGPU/sminmax.ll b/test/CodeGen/AMDGPU/sminmax.ll index bea3ac15f55..20f96fc63cc 100644 --- a/test/CodeGen/AMDGPU/sminmax.ll +++ b/test/CodeGen/AMDGPU/sminmax.ll @@ -128,3 +128,76 @@ define void @v_abs_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* % store <4 x i32> %res2, <4 x i32> addrspace(1)* %out, align 4 ret void } + +; FUNC-LABEL: {{^}}s_min_max_i32: +; GCN: s_load_dword [[VAL0:s[0-9]+]] +; GCN: s_load_dword [[VAL1:s[0-9]+]] + +; GCN-DAG: s_min_i32 s{{[0-9]+}}, [[VAL0]], [[VAL1]] +; GCN-DAG: s_max_i32 s{{[0-9]+}}, [[VAL0]], [[VAL1]] +define void @s_min_max_i32(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 %val0, i32 %val1) nounwind { + %cond0 = icmp sgt i32 %val0, %val1 + %sel0 = select i1 %cond0, i32 %val0, i32 %val1 + %sel1 = select i1 %cond0, i32 %val1, i32 %val0 + + store volatile i32 %sel0, i32 addrspace(1)* %out0, align 4 + store volatile i32 %sel1, i32 addrspace(1)* %out1, align 4 + ret void +} + +; FUNC-LABEL: {{^}}v_min_max_i32: +; GCN: buffer_load_dword [[VAL0:v[0-9]+]] +; GCN: buffer_load_dword [[VAL1:v[0-9]+]] + +; GCN-DAG: v_min_i32_e32 v{{[0-9]+}}, [[VAL1]], [[VAL0]] +; GCN-DAG: v_max_i32_e32 v{{[0-9]+}}, [[VAL1]], [[VAL0]] +define void @v_min_max_i32(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %ptr0, i32 addrspace(1)* %ptr1) nounwind { + %val0 = load volatile i32, i32 addrspace(1)* %ptr0 + %val1 = load volatile i32, i32 addrspace(1)* %ptr1 + + %cond0 = icmp sgt i32 %val0, %val1 + %sel0 = select i1 %cond0, i32 %val0, i32 %val1 + %sel1 = select i1 %cond0, i32 %val1, i32 %val0 + + store volatile i32 %sel0, i32 addrspace(1)* %out0, align 4 + store volatile i32 %sel1, i32 addrspace(1)* %out1, align 4 + ret void +} + +; FUNC-LABEL: {{^}}s_min_max_v4i32: +; GCN-DAG: s_min_i32 +; GCN-DAG: s_min_i32 +; GCN-DAG: s_min_i32 +; GCN-DAG: s_min_i32 +; GCN-DAG: s_max_i32 +; GCN-DAG: s_max_i32 +; GCN-DAG: s_max_i32 +; GCN-DAG: s_max_i32 +define void @s_min_max_v4i32(<4 x i32> addrspace(1)* %out0, <4 x i32> addrspace(1)* %out1, <4 x i32> %val0, <4 x i32> %val1) nounwind { + %cond0 = icmp sgt <4 x i32> %val0, %val1 + %sel0 = select <4 x i1> %cond0, <4 x i32> %val0, <4 x i32> %val1 + %sel1 = select <4 x i1> %cond0, <4 x i32> %val1, <4 x i32> %val0 + + store volatile <4 x i32> %sel0, <4 x i32> addrspace(1)* %out0, align 4 + store volatile <4 x i32> %sel1, <4 x i32> addrspace(1)* %out1, align 4 + ret void +} + +; FUNC-LABEL: {{^}}v_min_max_i32_user: +; GCN: v_cmp_gt_i32_e32 +; GCN-DAG: v_cndmask_b32_e32 +; GCN-DAG: v_cndmask_b32_e32 +; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc +define void @v_min_max_i32_user(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %ptr0, i32 addrspace(1)* %ptr1) nounwind { + %val0 = load volatile i32, i32 addrspace(1)* %ptr0 + %val1 = load volatile i32, i32 addrspace(1)* %ptr1 + + %cond0 = icmp sgt i32 %val0, %val1 + %sel0 = select i1 %cond0, i32 %val0, i32 %val1 + %sel1 = select i1 %cond0, i32 %val1, i32 %val0 + + store volatile i32 %sel0, i32 addrspace(1)* %out0, align 4 + store volatile i32 %sel1, i32 addrspace(1)* %out1, align 4 + store volatile i1 %cond0, i1 addrspace(1)* undef + ret void +}