From: Nicolai Haehnle <nhaehnle@gmail.com>
Date: Mon, 23 Apr 2018 13:06:03 +0000 (+0000)
Subject: AMDGPU: Fix SDWA peephole for V_AND_B32
X-Git-Tag: android-x86-7.1-r4~2012
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=3db53ca6545270dc0ac224b9c0a682cc57ba0b28;p=android-x86%2Fexternal-llvm.git

AMDGPU: Fix SDWA peephole for V_AND_B32

Summary:
Found by inspection. We care about the operand that *doesn't*
contain the immediate.

I believe this is currently not hit because we fold 0xff / 0xffff
immediates only later.

Change-Id: Ic3cf8538bc7da5eff3200d96eccf9d339e6345a7

Reviewers: arsenm, rampitec

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D45886

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330586 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/SIPeepholeSDWA.cpp b/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
index 648f97a1518..3da63ac8691 100644
--- a/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
+++ b/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
@@ -699,7 +699,7 @@ SIPeepholeSDWA::matchSDWAOperand(MachineInstr &MI) {
 
     MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
 
-    if (TRI->isPhysicalRegister(Src1->getReg()) ||
+    if (TRI->isPhysicalRegister(ValSrc->getReg()) ||
         TRI->isPhysicalRegister(Dst->getReg()))
       break;