From: Thiemo Seufer Date: Mon, 19 Feb 2007 17:53:29 +0000 (+0000) Subject: * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=41ba6fa27106054ef998dbe61fe0fb3e57743032;p=pf3gnuchains%2Fpf3gnuchains3x.git * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2 jumps with hazard barrier. --- diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 9ff5dbb0dd..32d81c0c24 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,14 +1,20 @@ 2007-02-19 Thiemo Seufer Nigel Stephens + * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2 + jumps with hazard barrier. + +2007-02-19 Thiemo Seufer + Nigel Stephens + * interp.c (sim_monitor): Flush stdout and stderr file descriptors after each call to sim_io_write. -2007-02-19 Thiemo Seufer +2007-02-19 Thiemo Seufer Nigel Stephens - - (ColdReset): Set CP0 Config0 to reflect the address size supported - by this simulator. + + * interp.c (ColdReset): Set CP0 Config0 to reflect the address size + supported by this simulator. (decode_coproc): Recognise additional CP0 Config registers correctly. diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 6109589539..93f4f2d9a6 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -1945,8 +1945,18 @@ DELAY_SLOT (temp); } +000000,5.RS,00000,5.RD,10000,001001:SPECIAL:32::JALR_HB +"jalr.hb r":RD == 31 +"jalr.hb r, r" +*mips32r2: +*mips64r2: +{ + address_word temp = GPR[RS]; + GPR[RD] = CIA + 8; + DELAY_SLOT (temp); +} -000000,5.RS,000000000000000,001000:SPECIAL:32::JR +000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR "jr r" *mipsI: *mipsII: @@ -1964,6 +1974,13 @@ DELAY_SLOT (GPR[RS]); } +000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB +"jr.hb r" +*mips32r2: +*mips64r2: +{ + DELAY_SLOT (GPR[RS]); +} :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset {