From: Rob Clark <robdclark@chromium.org>
Date: Thu, 25 Jul 2019 22:25:22 +0000 (-0700)
Subject: freedreno: update registers
X-Git-Tag: android-x86-9.0-r1~3496
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=44f3c1cf01167c599d40f6ac35152b406cfbd51d;p=android-x86%2Fexternal-mesa.git

freedreno: update registers

Pull in some updates of VSC regs

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
---

diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml
index a001c9ae631..6868ed5528b 100644
--- a/src/freedreno/registers/a6xx.xml
+++ b/src/freedreno/registers/a6xx.xml
@@ -1771,6 +1771,16 @@ to upconvert to 32b float internally?
 	TODO now there seem to be two buffers of VSC data (both referenced by
 	CP_SET_BIN_DATA packet.  Not sure what this new DATA2 one is, but seems
 	to have the larger pitch.
+
+	The "DATA2" buffer is probably actually the main visibility stream; it
+	is at least the larger of the two.
+
+	For VSC_DATA_PITCH, 0x20 actually seems to be sufficient (although blob
+	uses something somewhat larger) for many cases, although required value
+	can ramp up somewhat higher.  Values less than 0x20 trigger GPU hangs
+	even with small amount of geometry (so possibly 0x20 is minimum
+	alignment or something like that).  So far I can't seem to find any-
+	thing that needs values larger than 0x20
 	 -->
 	<reg32 offset="0x0c30" name="VSC_PIPE_DATA2_ADDRESS_LO"/>
 	<reg32 offset="0x0c31" name="VSC_PIPE_DATA2_ADDRESS_HI"/>
@@ -1781,10 +1791,25 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x0c36" name="VSC_PIPE_DATA_PITCH"/>
 	<reg32 offset="0x0c37" name="VSC_PIPE_DATA_ARRAY_PITCH" shr="4" type="uint"/>
 
-	<!--
-	note, also a range starting at 0x0c58, one or the other probably
-	corresponds to the new "VSC_XXX" thing, whatever it is..
-	 -->
+	<array offset="0x0c38" name="VSC_STATE" stride="1" length="32">
+		<doc>
+			Seems to be a bitmap of which tiles mapped to the VSC
+			pipe contain geometry.
+
+			I suppose we can connect a maximum of 32 tiles to a
+			single VSC pipe.
+		</doc>
+		<reg32 offset="0x0" name="REG"/>
+	</array>
+
+	<array offset="0x0c58" name="VSC_SIZE2" stride="1" length="32">
+		<doc>
+			Has the size of data written to corresponding VSC_DATA2
+			buffer.
+		</doc>
+		<reg32 offset="0x0" name="REG"/>
+	</array>
+
 	<array offset="0x0c78" name="VSC_SIZE" stride="1" length="32">
 		<doc>
 			Has the size of data written to corresponding VSC pipe, ie.
diff --git a/src/freedreno/registers/adreno_pm4.xml b/src/freedreno/registers/adreno_pm4.xml
index dfb50bfdaf9..06175d3e1ad 100644
--- a/src/freedreno/registers/adreno_pm4.xml
+++ b/src/freedreno/registers/adreno_pm4.xml
@@ -41,6 +41,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<value name="LRZ_FLUSH" value="38" variants="A5XX,A6XX"/>
 	<value name="UNK_2C" value="44" variants="A5XX"/>
 	<value name="UNK_2D" value="45" variants="A5XX"/>
+
+	<!-- a6xx events -->
+	<value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>
 </enum>
 
 <enum name="pc_di_primtype">
@@ -1156,5 +1159,15 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
 	</reg32>
 </domain>
 
+<!-- I *think* this existed at least as far back as a4xx -->
+<domain name="CP_COND_REG_EXEC" width="32">
+	<reg32 offset="0" name="0">
+		<bitfield name="UNK28" pos="28" type="boolean"/>
+	</reg32>
+	<reg32 offset="1" name="1">
+		<bitfield name="DWORDS" low="0" high="31" type="uint"/>
+	</reg32>
+</domain>
+
 </database>