From: Prasad Sodagudi <psodagud@codeaurora.org>
Date: Tue, 28 Jul 2015 04:31:04 +0000 (+0530)
Subject: ARM: dts: msm: Add qcom,dump-size entry for dumping CPU L1/L2 caches
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=488460b4152924659d24d4a8e7043ec4568a4738;p=sagit-ice-cold%2Fkernel_xiaomi_msm8998.git

ARM: dts: msm: Add qcom,dump-size entry for dumping CPU L1/L2 caches

Update arm cache documentation about qcom,dump-size to dump
the CPU L1/L2 caches in order to analyze data corruption.

Change-Id: Ia9350b9c7810db7eb900957b4ce5dac046ab5e0d
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
---

diff --git a/Documentation/devicetree/bindings/arm/cache.txt b/Documentation/devicetree/bindings/arm/cache.txt
index b27cedf485f8..a9594f026506 100644
--- a/Documentation/devicetree/bindings/arm/cache.txt
+++ b/Documentation/devicetree/bindings/arm/cache.txt
@@ -64,6 +64,14 @@ This document provides the device tree bindings for ARM architected caches.
 			    bindings of power controller specified by the
 			    phandle [5].
 
+	- qcom,dump-size
+		Usage: Optional
+		Value type: <integer>
+		Definition: The memory size needed to contain a copy of the
+			    cache data and associated tag ram.
+			    size = nways * nsets * (bytes per cache line +
+			                            bytes tag ram per line)
+
 Example(dual-cluster big.LITTLE system 32-bit)
 
 	cpus {