From: astoria-d Date: Fri, 30 Aug 2013 03:13:19 +0000 (+0900) Subject: apu device integrated on the cpu port. X-Git-Tag: motonesfpga-gate-0.2.0~182 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=4a0cbb689f48c64a509fab58f8ba9895bc3eb3ec;p=motonesfpga%2Fmotonesfpga.git apu device integrated on the cpu port. --- diff --git a/simulation/address_decoder.vhd b/simulation/address_decoder.vhd index 1bbf980..e3519c8 100644 --- a/simulation/address_decoder.vhd +++ b/simulation/address_decoder.vhd @@ -8,7 +8,8 @@ generic (abus_size : integer := 16; dbus_size : integer := 8); R_nW : in std_logic; -- active high on read / active low on write. addr : in std_logic_vector (abus_size - 1 downto 0); d_io : inout std_logic_vector (dbus_size - 1 downto 0); - ppu_ce_n : out std_logic + ppu_ce_n : out std_logic; + apu_ce_n : out std_logic ); end address_decoder; @@ -51,9 +52,6 @@ architecture rtl of address_decoder is signal ram_oe_n : std_logic; signal ram_io : std_logic_vector (dsize - 1 downto 0); - signal apu_ce_n : std_logic; - signal apu_io : std_logic_vector (dsize - 1 downto 0); - begin rom_ce_n <= '0' when (addr(15) = '1' and R_nW = '1') else @@ -69,15 +67,9 @@ begin port map (ram_ce_n, ram_oe_n, R_nW, addr(ram_2k - 1 downto 0), ram_io); - ---dummy value. - apu_io <= "00000000"; - --must explicitly drive to for inout port. d_io <= ram_io when (((addr(15) or addr(14) or addr(13)) = '0') and r_nw = '1') else - apu_io - when ((addr(15) = '0') and (addr(14) = '1') and addr(13) = '0' - and r_nw = '1') else rom_out when ((addr(15) = '1') and r_nw = '1') else (others => 'Z'); @@ -87,6 +79,10 @@ begin when (addr(15) = '0' and addr(14) = '0' and addr(13) = '1') else '1'; + apu_ce_n <= '0' + when (addr(15) = '0' and addr(14) = '1' and addr(13) = '0') else + '1'; + --ram io timing. main_p : process (phi2, addr, d_io, R_nW) begin diff --git a/simulation/apu/apu.vhd b/simulation/apu/apu.vhd index 8be748d..6ba6db3 100644 --- a/simulation/apu/apu.vhd +++ b/simulation/apu/apu.vhd @@ -6,10 +6,11 @@ entity apu is ce_n : in std_logic; rst_n : in std_logic; r_nw : in std_logic; - cpu_addr : in std_logic_vector (2 downto 0); + cpu_addr : in std_logic_vector (4 downto 0); cpu_d : inout std_logic_vector (7 downto 0); vram_ad : inout std_logic_vector (7 downto 0); - vram_a : out std_logic_vector (13 downto 8) + vram_a : out std_logic_vector (13 downto 8); + rdy : out std_logic ); end apu; @@ -55,6 +56,8 @@ end procedure; constant dsize : integer := 8; +constant OAM_DMA : std_logic_vector(4 downto 0) := "10100"; + signal clk_n : std_logic; @@ -78,13 +81,13 @@ begin if (rst_n = '1' and ce_n = '0') then --- if(cpu_addr = PPUCTRL) then --- ppu_ctrl_we_n <= '0'; --- else --- ppu_ctrl_we_n <= '1'; --- end if; - + if(cpu_addr = OAM_DMA) then + rdy <= '0'; + else + rdy <= '1'; + end if; else + rdy <= '1'; end if; --if (rst_n = '1' and ce_n = '0') end process; diff --git a/simulation/motones_sim.vhd b/simulation/motones_sim.vhd index 0ec8e9c..5fc1584 100644 --- a/simulation/motones_sim.vhd +++ b/simulation/motones_sim.vhd @@ -45,7 +45,8 @@ architecture rtl of motones_sim is R_nW : in std_logic; addr : in std_logic_vector (abus_size - 1 downto 0); d_io : inout std_logic_vector (dbus_size - 1 downto 0); - ppu_ce_n : out std_logic + ppu_ce_n : out std_logic; + apu_ce_n : out std_logic ); end component; @@ -93,6 +94,19 @@ architecture rtl of motones_sim is ); end component; + component apu + port ( clk : in std_logic; + ce_n : in std_logic; + rst_n : in std_logic; + r_nw : in std_logic; + cpu_addr : in std_logic_vector (4 downto 0); + cpu_d : inout std_logic_vector (7 downto 0); + vram_ad : inout std_logic_vector (7 downto 0); + vram_a : out std_logic_vector (13 downto 8); + rdy : out std_logic + ); + end component; + ---clock frequency = 21,477,270 (21 MHz) constant base_clock_time : time := 46 ns; constant vga_clk_time : time := 40 ns; @@ -110,6 +124,7 @@ architecture rtl of motones_sim is signal d_io : std_logic_vector( data_size - 1 downto 0); signal ppu_ce_n : std_logic; + signal apu_ce_n : std_logic; signal rd_n : std_logic; signal wr_n : std_logic; signal ale : std_logic; @@ -129,7 +144,6 @@ architecture rtl of motones_sim is begin irq_n <= '0'; - rdy <= '1'; --- generate base clock. clock_p: process @@ -159,7 +173,7 @@ begin phi1, phi2, addr, d_io); addr_dec_inst : address_decoder generic map (addr_size, data_size) - port map (phi2, r_nw, addr, d_io, ppu_ce_n); + port map (phi2, r_nw, addr, d_io, ppu_ce_n, apu_ce_n); --nes ppu instance ppu_inst : ppu @@ -170,6 +184,10 @@ begin ppu_addr_decoder : v_address_decoder generic map (size14, data_size) port map (ppu_clk, rd_n, wr_n, ale, vram_ad, vram_a); + apu_inst : apu + port map (cpu_clk, apu_ce_n, rst_n, r_nw, addr(4 downto 0), d_io, + vram_ad, vram_a, rdy); + dummy_vga_disp : vga_device port map (vga_clk, rst_n, h_sync_n, v_sync_n, r, g, b);