From: Chris Lattner <sabre@nondot.org>
Date: Fri, 6 Oct 2006 17:34:12 +0000 (+0000)
Subject: Fix a miscompilation of:
X-Git-Tag: android-x86-6.0-r1~1003^2~40416
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=4bdd2753db4a9d92b64c68b042c8b38f7223238d;p=android-x86%2Fexternal-llvm.git

Fix a miscompilation of:

long long foo(long long X) {
  return (long long)(signed char)(int)X;
}

Instead of:

_foo:
        extsb r2, r4
        srawi r3, r4, 31
        mr r4, r2
        blr

we now produce:

_foo:
        extsb r4, r4
        srawi r3, r4, 31
        blr

This fixes a miscompilation in ConstantFolding.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30768 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 3a956d0f9bb..fc14b062aae 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -4349,12 +4349,14 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     
   case ISD::SIGN_EXTEND_INREG:
     ExpandOp(Node->getOperand(0), Lo, Hi);
-    // Sign extend the lo-part.
+    // sext_inreg the low part if needed.
+    Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
+    
+    // The high part gets the sign extension from the lo-part.  This handles
+    // things like sextinreg V:i64 from i8.
     Hi = DAG.getNode(ISD::SRA, NVT, Lo,
                      DAG.getConstant(MVT::getSizeInBits(NVT)-1,
                                      TLI.getShiftAmountTy()));
-    // sext_inreg the low part if needed.
-    Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
     break;
 
   case ISD::BSWAP: {