From: Rex Zhu <Rex.Zhu@amd.com>
Date: Tue, 10 Jan 2017 12:00:40 +0000 (+0800)
Subject: drm/amdgpu: fix bug set incorrect value to vce register
X-Git-Tag: android-x86-7.1-r1~6^2~39^2~48
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=4ee340c06bf2b271641cf08792c5173f55736184;p=android-x86%2Fkernel.git

drm/amdgpu: fix bug set incorrect value to vce register


[ Upstream commit e05208ded1905e500cd5b369d624b071951c68b9 ]

Set the proper bits for clockgating setup.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 50f0cf2788b7..7522f796f19b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -182,7 +182,7 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
 		WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
 
 		data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
-		data &= ~0xffc00000;
+		data &= ~0x3ff;
 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
 
 		data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);