From: Sanjay Patel <spatel@rotateright.com>
Date: Wed, 30 Sep 2015 22:25:55 +0000 (+0000)
Subject: [x86] enable machine combiner reassociations for 256-bit vector logical integer insts
X-Git-Tag: android-x86-7.1-r4~43135
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=4f55287fa6b7810e1845f606f0d2929d1192a50a;p=android-x86%2Fexternal-llvm.git

[x86] enable machine combiner reassociations for 256-bit vector logical integer insts


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248955 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 4a8bedceb49..71b5ab4770a 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -6373,8 +6373,11 @@ bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
   case X86::PORrr:
   case X86::PXORrr:
   case X86::VPANDrr:
+  case X86::VPANDYrr:
   case X86::VPORrr:
+  case X86::VPORYrr:
   case X86::VPXORrr:
+  case X86::VPXORYrr:
   // Normal min/max instructions are not commutative because of NaN and signed
   // zero semantics, but these are. Thus, there's no need to check for global
   // relaxed math; the instructions themselves have the properties we need.
diff --git a/test/CodeGen/X86/machine-combiner-int-vec.ll b/test/CodeGen/X86/machine-combiner-int-vec.ll
index 8316f66c1dc..dc1ce77e13b 100644
--- a/test/CodeGen/X86/machine-combiner-int-vec.ll
+++ b/test/CodeGen/X86/machine-combiner-int-vec.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse < %s | FileCheck %s --check-prefix=SSE
-; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=avx < %s | FileCheck %s --check-prefix=AVX
+; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse2 < %s | FileCheck %s --check-prefix=SSE
+; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=avx2 < %s | FileCheck %s --check-prefix=AVX
 
 ; Verify that 128-bit vector logical ops are reassociated.
 
@@ -66,3 +66,47 @@ define <4 x i32> @reassociate_xor_v4i32(<4 x i32> %x0, <4 x i32> %x1, <4 x i32>
   ret <4 x i32> %t2
 }
 
+; Verify that 256-bit vector logical ops are reassociated.
+
+define <8 x i32> @reassociate_and_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) {
+; AVX-LABEL: reassociate_and_v8i32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpand %ymm3, %ymm2, %ymm1
+; AVX-NEXT:    vpand %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    retq
+
+  %t0 = add <8 x i32> %x0, %x1
+  %t1 = and <8 x i32> %x2, %t0
+  %t2 = and <8 x i32> %x3, %t1
+  ret <8 x i32> %t2
+}
+
+define <8 x i32> @reassociate_or_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) {
+; AVX-LABEL: reassociate_or_v8i32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpor %ymm3, %ymm2, %ymm1
+; AVX-NEXT:    vpor %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    retq
+
+  %t0 = add <8 x i32> %x0, %x1
+  %t1 = or <8 x i32> %x2, %t0
+  %t2 = or <8 x i32> %x3, %t1
+  ret <8 x i32> %t2
+}
+
+define <8 x i32> @reassociate_xor_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) {
+; AVX-LABEL: reassociate_xor_v8i32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpxor %ymm3, %ymm2, %ymm1
+; AVX-NEXT:    vpxor %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    retq
+
+  %t0 = add <8 x i32> %x0, %x1
+  %t1 = xor <8 x i32> %x2, %t0
+  %t2 = xor <8 x i32> %x3, %t1
+  ret <8 x i32> %t2
+}
+