From: Brahmaji K <bkomma@codeaurora.org>
Date: Tue, 4 Oct 2016 09:07:06 +0000 (+0530)
Subject: ARM: dts: msm: Add qseecom device node for msmfalcon
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=52ab253870978e80ca86c207b31019bb8d76a1f2;p=sagit-ice-cold%2Fkernel_xiaomi_msm8998.git

ARM: dts: msm: Add qseecom device node for msmfalcon

Add qseecom device node with all the necessary parameters,
to enable qseecom driver on msmfalcon.

Change-Id: Ib29962ebc7427391d7c0e355fa46156d2a8d15e5
Signed-off-by: Brahmaji K <bkomma@codeaurora.org>
---

diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi
index ed8bee03b4d0..23547022b998 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi
+++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi
@@ -1206,6 +1206,34 @@
 		qcom,irq-is-percpu;
 		interrupts = <1 6 4>;
 	};
+
+	qcom_seecom: qseecom@86d00000 {
+		compatible = "qcom,qseecom";
+		reg = <0x86d00000 0x2200000>;
+		reg-names = "secapp-region";
+		qcom,hlos-num-ce-hw-instances = <1>;
+		qcom,hlos-ce-hw-instance = <0>;
+		qcom,qsee-ce-hw-instance = <0>;
+		qcom,disk-encrypt-pipe-pair = <2>;
+		qcom,support-fde;
+		qcom,no-clock-support;
+		qcom,msm-bus,name = "qseecom-noc";
+		qcom,msm-bus,num-cases = <4>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps =
+			<55 512 0 0>,
+			<55 512 200000 400000>,
+			<55 512 300000 800000>,
+			<55 512 400000 1000000>;
+		clock-names = "core_clk_src", "core_clk",
+				"iface_clk", "bus_clk";
+		clocks = <&clock_gcc QSEECOM_CE1_CLK>,
+			<&clock_gcc QSEECOM_CE1_CLK>,
+			<&clock_gcc QSEECOM_CE1_CLK>,
+			<&clock_gcc QSEECOM_CE1_CLK>;
+		qcom,ce-opp-freq = <171430000>;
+		qcom,qsee-reentrancy-support = <2>;
+	};
 };
 
 #include "msmfalcon-ion.dtsi"