From: Manoj Gupta <manojgupta@google.com>
Date: Thu, 5 Apr 2018 22:47:25 +0000 (+0000)
Subject: Attempt to fix Mips breakages.
X-Git-Tag: android-x86-7.1-r4~2714
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=55b03d2669109df611cbe1d05f3926373c72f0c3;p=android-x86%2Fexternal-llvm.git

Attempt to fix Mips breakages.

Summary:
Replace ArrayRefs by actual std::array objects so that there are
no dangling references.

Reviewers: rsmith, gkistanova

Subscribers: sdardis, arichardson, llvm-commits

Differential Revision: https://reviews.llvm.org/D45338

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329359 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Mips/MipsFastISel.cpp b/lib/Target/Mips/MipsFastISel.cpp
index 85bd565571c..ac1f9c5129b 100644
--- a/lib/Target/Mips/MipsFastISel.cpp
+++ b/lib/Target/Mips/MipsFastISel.cpp
@@ -67,6 +67,7 @@
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>
+#include <array>
 #include <cassert>
 #include <cstdint>
 
@@ -1306,13 +1307,13 @@ bool MipsFastISel::fastLowerArguments() {
     return false;
   }
 
-  const ArrayRef<MCPhysReg> GPR32ArgRegs = {Mips::A0, Mips::A1, Mips::A2,
-                                            Mips::A3};
-  const ArrayRef<MCPhysReg> FGR32ArgRegs = {Mips::F12, Mips::F14};
-  const ArrayRef<MCPhysReg> AFGR64ArgRegs = {Mips::D6, Mips::D7};
-  ArrayRef<MCPhysReg>::iterator NextGPR32 = GPR32ArgRegs.begin();
-  ArrayRef<MCPhysReg>::iterator NextFGR32 = FGR32ArgRegs.begin();
-  ArrayRef<MCPhysReg>::iterator NextAFGR64 = AFGR64ArgRegs.begin();
+  std::array<MCPhysReg, 4> GPR32ArgRegs = {Mips::A0, Mips::A1, Mips::A2,
+                                           Mips::A3};
+  std::array<MCPhysReg, 2> FGR32ArgRegs = {Mips::F12, Mips::F14};
+  std::array<MCPhysReg, 2> AFGR64ArgRegs = {Mips::D6, Mips::D7};
+  auto NextGPR32 = GPR32ArgRegs.begin();
+  auto NextFGR32 = FGR32ArgRegs.begin();
+  auto NextAFGR64 = AFGR64ArgRegs.begin();
 
   struct AllocatedReg {
     const TargetRegisterClass *RC;