From: Kenneth Graunke Date: Tue, 1 Aug 2017 05:04:25 +0000 (-0700) Subject: i965: Delete pitch alignment assertion in get_blit_intratile_offset_el. X-Git-Tag: android-x86-8.1-r1~10916 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=595a47b8293b1d97a3ae7dbfa8db703bfb4e7aae;p=android-x86%2Fexternal-mesa.git i965: Delete pitch alignment assertion in get_blit_intratile_offset_el. The cacheline alignment restriction is on the base address; the pitch can be anything. Fixes assertion failures when using primus (say, on glxgears, which creates a 300x300 linear BGRX surface with a pitch of 1200): intel_blit.c:190: get_blit_intratile_offset_el: Assertion `mt->surf.row_pitch % 64 == 0' failed. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Chris Wilson --- diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index eca87368047..b1db7aa2293 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -187,7 +187,6 @@ get_blit_intratile_offset_el(const struct brw_context *brw, * The offsets we get from ISL in the tiled case are already aligned. * In the linear case, we need to do some of our own aligning. */ - assert(mt->surf.row_pitch % 64 == 0); uint32_t delta = *base_address_offset & 63; assert(delta % mt->cpp == 0); *base_address_offset -= delta;