From: ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Mon, 2 Jun 2008 07:15:18 +0000 (+0000)
Subject: Proper sign extensions for 32-bit divisions, spotted by Richard Sandiford.
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=619dfca13a76da9bd10766858ed3ba40d4b303b2;p=qmiga%2Fqemu.git

Proper sign extensions for 32-bit divisions, spotted by Richard Sandiford.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4650 c046a42c-6fe2-441c-8c8c-71466251a162
---

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 3ff7aec864..e3481e49d5 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1900,6 +1900,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
         {
             int l1 = gen_new_label();
 
+            tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+            tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
             {
                 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
@@ -1912,6 +1914,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
                 tcg_gen_rem_i64(r_tmp2, r_tmp1, r_tmp2);
                 tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp3);
                 tcg_gen_trunc_i64_tl(cpu_T[1], r_tmp2);
+                tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+                tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
                 gen_store_LO(cpu_T[0], 0);
                 gen_store_HI(cpu_T[1], 0);
             }
@@ -1923,6 +1927,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
         {
             int l1 = gen_new_label();
 
+            tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
             {
                 TCGv r_tmp1 = new_tmp();
@@ -1962,8 +1967,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
             {
                 int l2 = gen_new_label();
 
-                tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], 1ULL << 63, l2);
-                tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[1], -1ULL, l2);
+                tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], -1LL << 63, l2);
+                tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[1], -1LL, l2);
                 {
                     tcg_gen_movi_tl(cpu_T[1], 0);
                     gen_store_LO(cpu_T[0], 0);