From: Qipan Li Date: Mon, 14 Apr 2014 06:29:58 +0000 (+0800) Subject: spi: sirf: set SPI controller in RISC IO chipselect mode X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=625227a4e916fa87f1dd84bde518ef403c3f708a;p=sagit-ice-cold%2Fkernel_xiaomi_msm8998.git spi: sirf: set SPI controller in RISC IO chipselect mode SPI bitbang supply "chipselect" interface for change chip-select line , in the SiRFSoC SPI controller, we need to enable "SPI_CS_IO_MODE", otherwise, spi_sirfsoc_chipselect() has no effect. now the driver is working is because SPI controller will control CS automatically without SPI_CS_IO_MODE. this patch makes the CS controller really controlled by software. Signed-off-by: Qipan Li Signed-off-by: Barry Song Signed-off-by: Mark Brown --- diff --git a/drivers/spi/spi-sirf.c b/drivers/spi/spi-sirf.c index 51d7c988d3ae..9b30743d816a 100644 --- a/drivers/spi/spi-sirf.c +++ b/drivers/spi/spi-sirf.c @@ -559,6 +559,11 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t) regval &= ~SIRFSOC_SPI_CMD_MODE; sspi->tx_by_cmd = false; } + /* + * set spi controller in RISC chipselect mode, we are controlling CS by + * software BITBANG_CS_ACTIVE and BITBANG_CS_INACTIVE. + */ + regval |= SIRFSOC_SPI_CS_IO_MODE; writel(regval, sspi->base + SIRFSOC_SPI_CTRL); if (IS_DMA_VALID(t)) {