From: Paul Brook Date: Sun, 8 Oct 2006 18:44:07 +0000 (+0000) Subject: 2006-10-08 Paul Brook X-Git-Tag: insight_6_8-branchpoint~2759 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=683d35f2973f14c8057b5e37c018845f55c62dd3;p=pf3gnuchains%2Fpf3gnuchains4x.git 2006-10-08 Paul Brook gas/ * config/tc-arm.c (parse_big_immediate): 64-bit host fix. (parse_operands): Use parse_big_immediate for OP_NILO. (neon_cmode_for_logic_imm): Try smaller element sizes. (neon_cmode_for_move_imm): Ditto. (do_neon_logic): Handle .i64 pseudo-op. gas/testsuite/ * testsuite/gas/arm/neon-cov.s: Test pseudo-instruction forms of vmov, vmvn and logic immediate instructions. * testsuite/gas/arm/neon-cov.d: ditto. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 32bc1f7100..fd4d462b66 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,11 @@ +2006-10-08 Paul Brook + + * config/tc-arm.c (parse_big_immediate): 64-bit host fix. + (parse_operands): Use parse_big_immediate for OP_NILO. + (neon_cmode_for_logic_imm): Try smaller element sizes. + (neon_cmode_for_move_imm): Ditto. + (do_neon_logic): Handle .i64 pseudo-op. + 2006-09-29 Alan Modra * po/POTFILES.in: Regenerate. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 900fec66f1..64d75aa984 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -4013,7 +4013,7 @@ parse_immediate (char **str, int *val, int min, int max, } /* Less-generic immediate-value read function with the possibility of loading a - big (64-bit) immediate, as required by Neon VMOV and VMVN immediate + big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate instructions. Puts the result directly in inst.operands[i]. */ static int @@ -4025,7 +4025,18 @@ parse_big_immediate (char **str, int i) my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); if (exp.X_op == O_constant) - inst.operands[i].imm = exp.X_add_number; + { + inst.operands[i].imm = exp.X_add_number & 0xffffffff; + /* If we're on a 64-bit host, then a 64-bit number can be returned using + O_constant. We have to be careful not to break compilation for + 32-bit X_add_number, though. */ + if ((exp.X_add_number & ~0xffffffffl) != 0) + { + /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ + inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; + inst.operands[i].regisimm = 1; + } + } else if (exp.X_op == O_big && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64) @@ -5595,8 +5606,13 @@ parse_operands (char *str, const unsigned char *pattern) inst.operands[i-1].present = 0; break; try_imm: - /* Immediate gets verified properly later, so accept any now. */ - po_imm_or_fail (INT_MIN, INT_MAX, TRUE); + /* There's a possibility of getting a 64-bit immediate here, so + we need special handling. */ + if (parse_big_immediate (&str, i) == FAIL) + { + inst.error = _("immediate value is out of range"); + goto failure; + } } break; @@ -11397,45 +11413,52 @@ do_neon_qshl_imm (void) static int neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) { - /* Handle .I8 and .I64 as pseudo-instructions. */ - switch (size) + /* Handle .I8 pseudo-instructions. */ + if (size == 8) { - case 8: /* Unfortunately, this will make everything apart from zero out-of-range. FIXME is this the intended semantics? There doesn't seem much point in accepting .I8 if so. */ immediate |= immediate << 8; size = 16; - break; - case 64: - /* Similarly, anything other than zero will be replicated in bits [63:32], - which probably isn't want we want if we specified .I64. */ - if (immediate != 0) - goto bad_immediate; - size = 32; - break; - default: ; + } + + if (size >= 32) + { + if (immediate == (immediate & 0x000000ff)) + { + *immbits = immediate; + return 0x1; + } + else if (immediate == (immediate & 0x0000ff00)) + { + *immbits = immediate >> 8; + return 0x3; + } + else if (immediate == (immediate & 0x00ff0000)) + { + *immbits = immediate >> 16; + return 0x5; + } + else if (immediate == (immediate & 0xff000000)) + { + *immbits = immediate >> 24; + return 0x7; + } + if ((immediate & 0xffff) != (immediate >> 16)) + goto bad_immediate; + immediate &= 0xffff; } if (immediate == (immediate & 0x000000ff)) { *immbits = immediate; - return (size == 16) ? 0x9 : 0x1; + return 0x9; } else if (immediate == (immediate & 0x0000ff00)) { *immbits = immediate >> 8; - return (size == 16) ? 0xb : 0x3; - } - else if (immediate == (immediate & 0x00ff0000)) - { - *immbits = immediate >> 16; - return 0x5; - } - else if (immediate == (immediate & 0xff000000)) - { - *immbits = immediate >> 24; - return 0x7; + return 0xb; } bad_immediate: @@ -11476,7 +11499,8 @@ neon_qfloat_bits (unsigned imm) the instruction. *OP is passed as the initial value of the op field, and may be set to a different value depending on the constant (i.e. "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not - MVN). */ + MVN). If the immediate looks like a repeated parttern then also + try smaller element sizes. */ static int neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, unsigned *immbits, @@ -11489,63 +11513,87 @@ neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, unsigned *immbits, *immbits = neon_qfloat_bits (immlo); return 0xf; } - else if (size == 64 && neon_bits_same_in_bytes (immhi) - && neon_bits_same_in_bytes (immlo)) - { - /* Check this one first so we don't have to bother with immhi in later - tests. */ - if (*op == 1) - return FAIL; - *immbits = (neon_squash_bits (immhi) << 4) | neon_squash_bits (immlo); - *op = 1; - return 0xe; - } - else if (immhi != 0) - return FAIL; - else if (immlo == (immlo & 0x000000ff)) - { - /* 64-bit case was already handled. Don't allow MVN with 8-bit - immediate. */ - if ((size != 8 && size != 16 && size != 32) - || (size == 8 && *op == 1)) - return FAIL; - *immbits = immlo; - return (size == 8) ? 0xe : (size == 16) ? 0x8 : 0x0; - } - else if (immlo == (immlo & 0x0000ff00)) - { - if (size != 16 && size != 32) - return FAIL; - *immbits = immlo >> 8; - return (size == 16) ? 0xa : 0x2; - } - else if (immlo == (immlo & 0x00ff0000)) + + if (size == 64) { - if (size != 32) - return FAIL; - *immbits = immlo >> 16; - return 0x4; + if (neon_bits_same_in_bytes (immhi) + && neon_bits_same_in_bytes (immlo)) + { + if (*op == 1) + return FAIL; + *immbits = (neon_squash_bits (immhi) << 4) + | neon_squash_bits (immlo); + *op = 1; + return 0xe; + } + + if (immhi != immlo) + return FAIL; } - else if (immlo == (immlo & 0xff000000)) + + if (size >= 32) { - if (size != 32) - return FAIL; - *immbits = immlo >> 24; - return 0x6; + if (immlo == (immlo & 0x000000ff)) + { + *immbits = immlo; + return 0x0; + } + else if (immlo == (immlo & 0x0000ff00)) + { + *immbits = immlo >> 8; + return 0x2; + } + else if (immlo == (immlo & 0x00ff0000)) + { + *immbits = immlo >> 16; + return 0x4; + } + else if (immlo == (immlo & 0xff000000)) + { + *immbits = immlo >> 24; + return 0x6; + } + else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) + { + *immbits = (immlo >> 8) & 0xff; + return 0xc; + } + else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) + { + *immbits = (immlo >> 16) & 0xff; + return 0xd; + } + + if ((immlo & 0xffff) != (immlo >> 16)) + return FAIL; + immlo &= 0xffff; } - else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) + + if (size >= 16) { - if (size != 32) - return FAIL; - *immbits = (immlo >> 8) & 0xff; - return 0xc; + if (immlo == (immlo & 0x000000ff)) + { + *immbits = immlo; + return 0x8; + } + else if (immlo == (immlo & 0x0000ff00)) + { + *immbits = immlo >> 8; + return 0xa; + } + + if ((immlo & 0xff) != (immlo >> 8)) + return FAIL; + immlo &= 0xff; } - else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) + + if (immlo == (immlo & 0x000000ff)) { - if (size != 32) - return FAIL; - *immbits = (immlo >> 16) & 0xff; - return 0xd; + /* Don't allow MVN with 8-bit immediate. */ + if (*op == 1) + return FAIL; + *immbits = immlo; + return 0xe; } return FAIL; @@ -11628,28 +11676,37 @@ do_neon_logic (void) inst.instruction = NEON_ENC_IMMED (inst.instruction); + immbits = inst.operands[1].imm; + if (et.size == 64) + { + /* .i64 is a pseudo-op, so the immediate must be a repeating + pattern. */ + if (immbits != (inst.operands[1].regisimm ? + inst.operands[1].reg : 0)) + { + /* Set immbits to an invalid constant. */ + immbits = 0xdeadbeef; + } + } + switch (opcode) { case N_MNEM_vbic: - cmode = neon_cmode_for_logic_imm (inst.operands[1].imm, &immbits, - et.size); + cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); break; case N_MNEM_vorr: - cmode = neon_cmode_for_logic_imm (inst.operands[1].imm, &immbits, - et.size); + cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); break; case N_MNEM_vand: /* Pseudo-instruction for VBIC. */ - immbits = inst.operands[1].imm; neon_invert_size (&immbits, 0, et.size); cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); break; case N_MNEM_vorn: /* Pseudo-instruction for VORR. */ - immbits = inst.operands[1].imm; neon_invert_size (&immbits, 0, et.size); cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); break; diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 91a168e72f..8b5d64763e 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2006-10-08 Paul Brook + + * testsuite/gas/arm/neon-cov.s: Test pseudo-instruction forms of + vmov, vmvn and logic immediate instructions. + * testsuite/gas/arm/neon-cov.d: ditto. + 2006-09-28 Bridge Wu * gas/arm/iwmmxt-wldstbh.s: New file. diff --git a/gas/testsuite/gas/arm/neon-cov.d b/gas/testsuite/gas/arm/neon-cov.d index ca695d8eb2..a8c8e20bfb 100644 --- a/gas/testsuite/gas/arm/neon-cov.d +++ b/gas/testsuite/gas/arm/neon-cov.d @@ -278,6 +278,24 @@ Disassembly of section \.text: 0[0-9a-f]+ <[^>]+> f3000150 veor q0, q0, q0 0[0-9a-f]+ <[^>]+> f3000150 veor q0, q0, q0 0[0-9a-f]+ <[^>]+> f3000110 veor d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820135 vbic\.i32 d0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820335 vbic\.i32 d0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820535 vbic\.i32 d0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820735 vbic\.i32 d0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500 0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff 0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff 0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff @@ -296,12 +314,39 @@ Disassembly of section \.text: 0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000 0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000 0[0-9a-f]+ <[^>]+> f387073f vbic\.i32 d0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500 0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff 0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff 0[0-9a-f]+ <[^>]+> f387093f vbic\.i16 d0, #255 ; 0x00ff 0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00 0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00 0[0-9a-f]+ <[^>]+> f3870b3f vbic\.i16 d0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800930 vbic\.i16 d0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820115 vorr\.i32 d0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820315 vorr\.i32 d0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820515 vorr\.i32 d0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820715 vorr\.i32 d0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500 0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff 0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff 0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff @@ -320,12 +365,39 @@ Disassembly of section \.text: 0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000 0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000 0[0-9a-f]+ <[^>]+> f387071f vorr\.i32 d0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500 0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff 0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff 0[0-9a-f]+ <[^>]+> f387091f vorr\.i16 d0, #255 ; 0x00ff 0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00 0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00 0[0-9a-f]+ <[^>]+> f3870b1f vorr\.i16 d0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800910 vorr\.i16 d0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820135 vbic\.i32 d0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820335 vbic\.i32 d0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820535 vbic\.i32 d0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820735 vbic\.i32 d0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500 0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff 0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff 0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff @@ -344,12 +416,39 @@ Disassembly of section \.text: 0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000 0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000 0[0-9a-f]+ <[^>]+> f387073f vbic\.i32 d0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500 0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff 0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff 0[0-9a-f]+ <[^>]+> f387093f vbic\.i16 d0, #255 ; 0x00ff 0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00 0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00 0[0-9a-f]+ <[^>]+> f3870b3f vbic\.i16 d0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800930 vbic\.i16 d0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820115 vorr\.i32 d0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820315 vorr\.i32 d0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820515 vorr\.i32 d0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820715 vorr\.i32 d0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500 0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff 0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff 0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff @@ -368,12 +467,21 @@ Disassembly of section \.text: 0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000 0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000 0[0-9a-f]+ <[^>]+> f387071f vorr\.i32 d0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500 0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff 0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff 0[0-9a-f]+ <[^>]+> f387091f vorr\.i16 d0, #255 ; 0x00ff 0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00 0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00 0[0-9a-f]+ <[^>]+> f3870b1f vorr\.i16 d0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800910 vorr\.i16 d0, #0 ; 0x0000 0[0-9a-f]+ <[^>]+> f3100150 vbsl q0, q0, q0 0[0-9a-f]+ <[^>]+> f3100150 vbsl q0, q0, q0 0[0-9a-f]+ <[^>]+> f3100110 vbsl d0, d0, d0 @@ -1091,6 +1199,40 @@ Disassembly of section \.text: 0[0-9a-f]+ <[^>]+> f3810e31 vmov\.i64 d0, #0xff0000ff000000ff 0[0-9a-f]+ <[^>]+> f2810f51 vmov\.f32 q0, #4\.25 ; 0x40880000 0[0-9a-f]+ <[^>]+> f2810f11 vmov\.f32 d0, #4\.25 ; 0x40880000 +0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f3820855 vmov\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820815 vmov\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820a55 vmov\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820a15 vmov\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f3820855 vmov\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820815 vmov\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820a55 vmov\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820a15 vmov\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820055 vmov\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820015 vmov\.i32 d0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820255 vmov\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820215 vmov\.i32 d0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820455 vmov\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820415 vmov\.i32 d0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820655 vmov\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820615 vmov\.i32 d0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820c55 vmov\.i32 q0, #42495 ; 0x0000a5ff +0[0-9a-f]+ <[^>]+> f3820c15 vmov\.i32 d0, #42495 ; 0x0000a5ff +0[0-9a-f]+ <[^>]+> f3820d55 vmov\.i32 q0, #10878975 ; 0x00a5ffff +0[0-9a-f]+ <[^>]+> f3820d15 vmov\.i32 d0, #10878975 ; 0x00a5ffff +0[0-9a-f]+ <[^>]+> f285067a vmvn\.i32 q0, #1509949440 ; 0x5a000000 +0[0-9a-f]+ <[^>]+> f285063a vmvn\.i32 d0, #1509949440 ; 0x5a000000 0[0-9a-f]+ <[^>]+> f3b005c0 vmvn q0, q0 0[0-9a-f]+ <[^>]+> f3b005c0 vmvn q0, q0 0[0-9a-f]+ <[^>]+> f3b00580 vmvn d0, d0 diff --git a/gas/testsuite/gas/arm/neon-cov.s b/gas/testsuite/gas/arm/neon-cov.s index d3253acda7..079e896c25 100644 --- a/gas/testsuite/gas/arm/neon-cov.s +++ b/gas/testsuite/gas/arm/neon-cov.s @@ -112,28 +112,46 @@ .endm .macro logic_imm op opq + logic_imm_1 \op \opq 0x000000a5000000a5 .i64 + logic_imm_1 \op \opq 0x0000a5000000a500 .i64 + logic_imm_1 \op \opq 0x00a5000000a50000 .i64 + logic_imm_1 \op \opq 0xa5000000a5000000 .i64 + logic_imm_1 \op \opq 0x00a500a500a500a5 .i64 + logic_imm_1 \op \opq 0xa500a500a500a500 .i64 logic_imm_1 \op \opq 0x000000ff .i32 logic_imm_1 \op \opq 0x000000ff .s32 logic_imm_1 \op \opq 0x000000ff .u32 logic_imm_1 \op \opq 0x0000ff00 .i32 logic_imm_1 \op \opq 0x00ff0000 .i32 logic_imm_1 \op \opq 0xff000000 .i32 + logic_imm_1 \op \opq 0x00a500a5 .i32 + logic_imm_1 \op \opq 0xa500a500 .i32 logic_imm_1 \op \opq 0x00ff .i16 logic_imm_1 \op \opq 0xff00 .i16 + logic_imm_1 \op \opq 0x00 .i8 .endm logic_imm vbic vbicq logic_imm vorr vorrq .macro logic_inv_imm op opq + logic_imm_1 \op \opq 0xffffff5affffff5a .i64 + logic_imm_1 \op \opq 0xffff5affffff5aff .i64 + logic_imm_1 \op \opq 0xff5affffff5affff .i64 + logic_imm_1 \op \opq 0x5affffff5affffff .i64 + logic_imm_1 \op \opq 0xff5aff5aff5aff5a .i64 + logic_imm_1 \op \opq 0x5aff5aff5aff5aff .i64 logic_imm_1 \op \opq 0xffffff00 .i32 logic_imm_1 \op \opq 0xffffff00 .s32 logic_imm_1 \op \opq 0xffffff00 .u32 logic_imm_1 \op \opq 0xffff00ff .i32 logic_imm_1 \op \opq 0xff00ffff .i32 logic_imm_1 \op \opq 0x00ffffff .i32 + logic_imm_1 \op \opq 0xff5aff5a .i32 + logic_imm_1 \op \opq 0x5aff5aff .i32 logic_imm_1 \op \opq 0xff00 .i16 logic_imm_1 \op \opq 0x00ff .i16 + logic_imm_1 \op \opq 0xff .i8 .endm logic_inv_imm vand vandq @@ -440,6 +458,24 @@ mov_imm vmov 0xff0000ff000000ff .i64 mov_imm vmov 0x40880000 .f32 + mov_imm vmov 0xa5a5 .i16 + mov_imm vmvn 0xa5a5 .i16 + mov_imm vmov 0xa5a5a5a5 .i32 + mov_imm vmvn 0xa5a5a5a5 .i32 + mov_imm vmov 0x00a500a5 .i32 + mov_imm vmov 0xa500a500 .i32 + mov_imm vmov 0xa5a5a5a5a5a5a5a5 .i64 + mov_imm vmvn 0xa5a5a5a5a5a5a5a5 .i64 + mov_imm vmov 0x00a500a500a500a5 .i64 + mov_imm vmov 0xa500a500a500a500 .i64 + mov_imm vmov 0x000000a5000000a5 .i64 + mov_imm vmov 0x0000a5000000a500 .i64 + mov_imm vmov 0x00a5000000a50000 .i64 + mov_imm vmov 0xa5000000a5000000 .i64 + mov_imm vmov 0x0000a5ff0000a5ff .i64 + mov_imm vmov 0x00a5ffff00a5ffff .i64 + mov_imm vmov 0xa5ffffffa5ffffff .i64 + vmvn q0,q0 vmvnq q0,q0 vmvn d0,d0