From: Andrew V. Tischenko <andrew.v.tischenko@gmail.com>
Date: Mon, 23 Oct 2017 15:53:30 +0000 (+0000)
Subject: Update DPPD/DPPS instruction scheduling on btver2.
X-Git-Tag: android-x86-7.1-r4~9442
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=69a114112f3ecdef36338884d4fa30e6874c8f52;p=android-x86%2Fexternal-llvm.git

Update DPPD/DPPS instruction scheduling on btver2.
Differential Revision: https://reviews.llvm.org/D39046


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316334 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ScheduleBtVer2.td b/lib/Target/X86/X86ScheduleBtVer2.td
index 40e7345cdd2..2fe03963d69 100644
--- a/lib/Target/X86/X86ScheduleBtVer2.td
+++ b/lib/Target/X86/X86ScheduleBtVer2.td
@@ -371,6 +371,38 @@ def : WriteRes<WriteFence,  [JSAGU]>;
 def : WriteRes<WriteNop, []>;
 
 ////////////////////////////////////////////////////////////////////////////////
+// SSE4.1 instructions.
+////////////////////////////////////////////////////////////////////////////////
+
+def WriteDPPS: SchedWriteRes<[JFPU0, JFPU1]> {
+  let Latency = 11;
+  let ResourceCycles = [3,3];
+  let NumMicroOps = 5;
+}
+def : InstRW<[WriteDPPS], (instregex "(V)?DPPSrri")>;
+
+def WriteDPPSLd: SchedWriteRes<[JLAGU, JFPU0, JFPU1]> {
+  let Latency = 16;
+  let ResourceCycles = [1,3,3];
+  let NumMicroOps = 6;
+}
+def : InstRW<[WriteDPPSLd], (instregex "(V)?DPPSrmi")>;
+
+def WriteDPPD: SchedWriteRes<[JFPU0, JFPU1]> {
+  let Latency = 9;
+  let ResourceCycles = [3,3];
+  let NumMicroOps = 3;
+}
+def : InstRW<[WriteDPPD], (instregex "(V)?DPPDrri")>;
+
+def WriteDPPDLd: SchedWriteRes<[JLAGU, JFPU0, JFPU1]> {
+  let Latency = 14;
+  let ResourceCycles = [1,3,3];
+  let NumMicroOps = 3;
+}
+def : InstRW<[WriteDPPDLd], (instregex "(V)?DPPDrmi")>;
+
+////////////////////////////////////////////////////////////////////////////////
 // SSE4A instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
@@ -390,6 +422,20 @@ def : InstRW<[WriteINSERTQ], (instregex "INSERTQ")>;
 // AVX instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
+def WriteVDPPSY: SchedWriteRes<[JFPU1, JFPU0]> {
+  let Latency = 12;
+  let ResourceCycles = [6, 6];
+  let NumMicroOps = 10;
+}
+def : InstRW<[WriteVDPPSY], (instregex "VDPPSYrr")>;
+
+def WriteVDPPSYLd: SchedWriteRes<[JLAGU, JFPU1, JFPU0]> {
+  let Latency = 17;
+  let ResourceCycles = [1, 6, 6];
+  let NumMicroOps = 11;
+}
+def : InstRW<[WriteVDPPSYLd, ReadAfterLd], (instregex "VDPPSYrm")>;
+
 def WriteFAddY: SchedWriteRes<[JFPU0]> {
   let Latency = 3;
   let ResourceCycles = [2];
diff --git a/test/CodeGen/X86/avx-schedule.ll b/test/CodeGen/X86/avx-schedule.ll
index 36d7e2316c9..0e351bc0a33 100644
--- a/test/CodeGen/X86/avx-schedule.ll
+++ b/test/CodeGen/X86/avx-schedule.ll
@@ -1509,8 +1509,8 @@ define <8 x float> @test_dpps(<8 x float> %a0, <8 x float> %a1, <8 x float> *%a2
 ;
 ; BTVER2-LABEL: test_dpps:
 ; BTVER2:       # BB#0:
-; BTVER2-NEXT:    vdpps $7, %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
-; BTVER2-NEXT:    vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
+; BTVER2-NEXT:    vdpps $7, %ymm1, %ymm0, %ymm0 # sched: [12:6.00]
+; BTVER2-NEXT:    vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [17:6.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_dpps:
diff --git a/test/CodeGen/X86/sse41-schedule.ll b/test/CodeGen/X86/sse41-schedule.ll
index ab163bd2e99..c6986f29b4b 100644
--- a/test/CodeGen/X86/sse41-schedule.ll
+++ b/test/CodeGen/X86/sse41-schedule.ll
@@ -320,8 +320,8 @@ define <2 x double> @test_dppd(<2 x double> %a0, <2 x double> %a1, <2 x double>
 ;
 ; BTVER2-LABEL: test_dppd:
 ; BTVER2:       # BB#0:
-; BTVER2-NEXT:    vdppd $7, %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT:    vdppd $7, (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
+; BTVER2-NEXT:    vdppd $7, %xmm1, %xmm0, %xmm0 # sched: [9:3.00]
+; BTVER2-NEXT:    vdppd $7, (%rdi), %xmm0, %xmm0 # sched: [14:3.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_dppd:
@@ -381,8 +381,8 @@ define <4 x float> @test_dpps(<4 x float> %a0, <4 x float> %a1, <4 x float> *%a2
 ;
 ; BTVER2-LABEL: test_dpps:
 ; BTVER2:       # BB#0:
-; BTVER2-NEXT:    vdpps $7, %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT:    vdpps $7, (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
+; BTVER2-NEXT:    vdpps $7, %xmm1, %xmm0, %xmm0 # sched: [11:3.00]
+; BTVER2-NEXT:    vdpps $7, (%rdi), %xmm0, %xmm0 # sched: [16:3.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_dpps: