From: Ville Syrjälä Date: Wed, 11 Sep 2019 13:31:26 +0000 (+0300) Subject: drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=74689ddfb7574e2bf08c7206a4ab0dff04978b05;p=uclinux-h8%2Flinux.git drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk On tgl/bxt/glk the cdclk bypass frequency depends on the PLL reference clock. So let's read out the ref clock before we try to compute the bypass clock. Cc: Matt Roper Fixes: 71dc367e2bc3 ("drm/i915: Consolidate bxt/cnl/icl cdclk readout") Signed-off-by: Ville Syrjälä Reviewed-by: Matt Roper Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20190911133129.27466-1-ville.syrjala@linux.intel.com --- diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 13779b6029f5..6fc8e3c0cfba 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1351,6 +1351,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, u32 divider; int div; + bxt_de_pll_readout(dev_priv, cdclk_state); + if (INTEL_GEN(dev_priv) >= 12) cdclk_state->bypass = cdclk_state->ref / 2; else if (INTEL_GEN(dev_priv) >= 11) @@ -1358,7 +1360,6 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, else cdclk_state->bypass = cdclk_state->ref; - bxt_de_pll_readout(dev_priv, cdclk_state); if (cdclk_state->vco == 0) { cdclk_state->cdclk = cdclk_state->bypass; goto out;