From: Bin Meng Date: Tue, 28 Feb 2023 10:40:24 +0000 (+0800) Subject: target/riscv: Simplify {read, write}_pmpcfg() a little bit X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=77ad639cb1269ed19fe726edee7c20487b95f7d3;p=qmiga%2Fqemu.git target/riscv: Simplify {read, write}_pmpcfg() a little bit Use the register index that has already been calculated in the pmpcfg_csr_{read,write} call. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei Message-ID: <20230228104035.1879882-9-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt --- diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9264db6110..a3e0e5755c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3360,7 +3360,7 @@ static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, if (!check_pmp_reg_index(env, reg_index)) { return RISCV_EXCP_ILLEGAL_INST; } - *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); + *val = pmpcfg_csr_read(env, reg_index); return RISCV_EXCP_NONE; } @@ -3372,7 +3372,7 @@ static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, if (!check_pmp_reg_index(env, reg_index)) { return RISCV_EXCP_ILLEGAL_INST; } - pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); + pmpcfg_csr_write(env, reg_index, val); return RISCV_EXCP_NONE; }