From: Biao Huang Date: Mon, 14 Mar 2022 07:57:10 +0000 (+0800) Subject: arm64: dts: mt2712: update ethernet device node X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=79e1177809f2a18518e2013de4abe989ff3c1aa8;p=uclinux-h8%2Flinux.git arm64: dts: mt2712: update ethernet device node Since there are some changes in ethernet driver: update ethernet device node in dts to accommodate to it. 1. stmmac_probe_config_dt() in stmmac_platform.c will initialize specified parameters according to compatible string "snps,dwmac-4.20a", then, dwmac-mediatek.c can skip the initialization if add compatible string "snps,dwmac-4.20a" in eth device node. 2. commit 882007ed7832 ("net-next: dt-binding: dwmac-mediatek: add more description for RMII") added rmii internal support, we should add corresponding clocks/clocks-names in eth device node. 3. add "snps,reset-delays-us = <0 10000 10000>;" to ensure reset delay can meet PHY requirement. Signed-off-by: Biao Huang Signed-off-by: David S. Miller --- diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts index 7d369fdd3117..11aa135aa0f3 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -110,6 +110,7 @@ phy-handle = <ðernet_phy0>; mediatek,tx-delay-ps = <1530>; snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; + snps,reset-delays-us = <0 10000 10000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <ð_default>; pinctrl-1 = <ð_sleep>; diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index de16c0d80c30..a27b7628c5f7 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -726,7 +726,7 @@ }; eth: ethernet@1101c000 { - compatible = "mediatek,mt2712-gmac"; + compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a"; reg = <0 0x1101c000 0 0x1300>; interrupts = ; interrupt-names = "macirq"; @@ -734,15 +734,19 @@ clock-names = "axi", "apb", "mac_main", - "ptp_ref"; + "ptp_ref", + "rmii_internal"; clocks = <&pericfg CLK_PERI_GMAC>, <&pericfg CLK_PERI_GMAC_PCLK>, <&topckgen CLK_TOP_ETHER_125M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_SEL>; + <&topckgen CLK_TOP_ETHER_50M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_SEL>; + <&topckgen CLK_TOP_ETHER_50M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>, - <&topckgen CLK_TOP_APLL1_D3>; + <&topckgen CLK_TOP_APLL1_D3>, + <&topckgen CLK_TOP_ETHERPLL_50M>; power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>; mediatek,pericfg = <&pericfg>; snps,axi-config = <&stmmac_axi_setup>;