From: Prasad Sodagudi Date: Thu, 12 Jan 2017 18:11:39 +0000 (-0800) Subject: arm64: Potential rollover condition for timer counter X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=7b2f8ee7696e33566aa8e3ed523d70994184c7bc;p=sagit-ice-cold%2Fkernel_xiaomi_msm8998.git arm64: Potential rollover condition for timer counter There is potential rollover condition for CNTVCT and CNTPCT counters. So on any architecture timer counter read, if the least significant 32 bits are set, reread counter. CRs-Fixed: 1074621 Change-Id: I136a5f0ee04deeb74c03800d591e44fbd9b4dd39 Signed-off-by: Prasad Sodagudi --- diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h index fbe0ca31a99c..09eb5b463635 100644 --- a/arch/arm64/include/asm/arch_timer.h +++ b/arch/arm64/include/asm/arch_timer.h @@ -119,7 +119,14 @@ static inline u64 arch_counter_get_cntvct(void) u64 cval; isb(); +#if IS_ENABLED(CONFIG_MSM_TIMER_LEAP) +#define L32_BITS 0x00000000FFFFFFFF + do { + asm volatile("mrs %0, cntvct_el0" : "=r" (cval)); + } while ((cval & L32_BITS) == L32_BITS); +#else asm volatile("mrs %0, cntvct_el0" : "=r" (cval)); +#endif return cval; } diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 2eb5f0efae90..8bf3355e95db 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -158,6 +158,15 @@ config ARM_ARCH_TIMER_EVTSTREAM This must be disabled for hardware validation purposes to detect any hardware anomalies of missing events. +config MSM_TIMER_LEAP + bool "ARCH TIMER counter rollover" + default n + depends on ARM_ARCH_TIMER && ARM64 + help + This option enables a check for least significant 32 bits of + counter rollover. On every counter read if least significant + 32 bits are set, reread counter. + config ARM_GLOBAL_TIMER bool select CLKSRC_OF if OF