From: Hiroshi Inoue Date: Fri, 13 Apr 2018 11:37:06 +0000 (+0000) Subject: [NFC] fix trivial typos in comments X-Git-Tag: android-x86-7.1-r4~2364 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=7dc3d5f99ac927910a1f71030f5845ced8087396;p=android-x86%2Fexternal-llvm.git [NFC] fix trivial typos in comments "the the" -> "the", "we we" -> "we", etc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330006 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/Support/CrashRecoveryContext.h b/include/llvm/Support/CrashRecoveryContext.h index 702623187ae..7b3fd4f882e 100644 --- a/include/llvm/Support/CrashRecoveryContext.h +++ b/include/llvm/Support/CrashRecoveryContext.h @@ -54,7 +54,7 @@ public: /// Register cleanup handler, which is used when the recovery context is /// finished. - /// The recovery context owns the the handler. + /// The recovery context owns the handler. void registerCleanup(CrashRecoveryContextCleanup *cleanup); void unregisterCleanup(CrashRecoveryContextCleanup *cleanup); diff --git a/include/llvm/Support/Unicode.h b/include/llvm/Support/Unicode.h index 815484fb017..983acaf0363 100644 --- a/include/llvm/Support/Unicode.h +++ b/include/llvm/Support/Unicode.h @@ -60,7 +60,7 @@ bool isPrintable(int UCS); /// * 1 for each of the remaining characters. int columnWidthUTF8(StringRef Text); -/// Fold input unicode character according the the Simple unicode case folding +/// Fold input unicode character according the Simple unicode case folding /// rules. int foldCharSimple(int C); diff --git a/lib/CodeGen/MachinePipeliner.cpp b/lib/CodeGen/MachinePipeliner.cpp index 56d998a6bbc..f392b307059 100644 --- a/lib/CodeGen/MachinePipeliner.cpp +++ b/lib/CodeGen/MachinePipeliner.cpp @@ -1991,7 +1991,7 @@ void SwingSchedulerDAG::groupRemainingNodes(NodeSetType &NodeSets) { if (!NewSet.empty()) NodeSets.push_back(NewSet); - // Create new nodes sets with the connected nodes any any remaining node that + // Create new nodes sets with the connected nodes any remaining node that // has no predecessor. for (unsigned i = 0; i < SUnits.size(); ++i) { SUnit *SU = &SUnits[i]; diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp index 08299628c91..8b9447bf20c 100644 --- a/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/lib/Target/AMDGPU/SIISelLowering.cpp @@ -4188,7 +4188,7 @@ SDValue SITargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op, DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr); - // Make sure we we do any optimizations that will make it easier to fold + // Make sure we do any optimizations that will make it easier to fold // source modifiers before obscuring it with bit operations. // XXX - Why doesn't this get called when vector_shuffle is expanded? diff --git a/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/lib/Target/AMDGPU/SIShrinkInstructions.cpp index 994658dd3f8..a346e409cb3 100644 --- a/lib/Target/AMDGPU/SIShrinkInstructions.cpp +++ b/lib/Target/AMDGPU/SIShrinkInstructions.cpp @@ -443,7 +443,7 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) { // VCC, e.g. S_AND_B64 (vcc = V_CMP_...), (vcc = V_CMP_...) // // So, instead of forcing the instruction to write to VCC, we provide - // a hint to the register allocator to use VCC and then we we will run + // a hint to the register allocator to use VCC and then we will run // this pass again after RA and shrink it if it outputs to VCC. MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC); continue; diff --git a/lib/Target/Hexagon/HexagonNewValueJump.cpp b/lib/Target/Hexagon/HexagonNewValueJump.cpp index 344652f4778..1abf27fbd61 100644 --- a/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -522,7 +522,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { // operands, the following check on the kill flag would suffice. // if(!jmpInstr->getOperand(0).isKill()) break; - // This predicate register is live out out of BB + // This predicate register is live out of BB // this would only work if we can actually use Live // variable analysis on phy regs - but LLVM does not // provide LV analysis on phys regs. diff --git a/lib/Target/X86/X86FlagsCopyLowering.cpp b/lib/Target/X86/X86FlagsCopyLowering.cpp index a101f6b7127..c656c3c9757 100644 --- a/lib/Target/X86/X86FlagsCopyLowering.cpp +++ b/lib/Target/X86/X86FlagsCopyLowering.cpp @@ -707,7 +707,7 @@ void X86FlagsCopyLoweringPass::rewriteCondJmp( void X86FlagsCopyLoweringPass::rewriteCopy(MachineInstr &MI, MachineOperand &FlagUse, MachineInstr &CopyDefI) { - // Just replace this copy with the the original copy def. + // Just replace this copy with the original copy def. MRI->replaceRegWith(MI.getOperand(0).getReg(), CopyDefI.getOperand(0).getReg()); MI.eraseFromParent(); diff --git a/test/CodeGen/SPARC/vector-extract-elt.ll b/test/CodeGen/SPARC/vector-extract-elt.ll index 47f39d5b9fb..9a5ac6920c6 100644 --- a/test/CodeGen/SPARC/vector-extract-elt.ll +++ b/test/CodeGen/SPARC/vector-extract-elt.ll @@ -2,7 +2,7 @@ ; If computeKnownSignBits (in SelectionDAG) can do a simple -; look-thru for extractelement then we we know that the add will yield a +; look-thru for extractelement then we know that the add will yield a ; non-negative result. define i1 @test1(<4 x i16>* %in) { ; CHECK-LABEL: ! %bb.0: diff --git a/test/CodeGen/X86/pr29010.ll b/test/CodeGen/X86/pr29010.ll index a2d5ff69a35..070635ba449 100644 --- a/test/CodeGen/X86/pr29010.ll +++ b/test/CodeGen/X86/pr29010.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=i386-linux -mattr=+avx | FileCheck %s -; In i386 there are only 8 XMMs (xmm0-xmm7), make sure we we are not creating illegal XMM +; In i386 there are only 8 XMMs (xmm0-xmm7), make sure we are not creating illegal XMM define float @only_xmm0_7(i32 %arg) { top: tail call void asm sideeffect "", "~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{dirflag},~{fpsr},~{flags}"()