From: Eric Anholt <eric@anholt.net>
Date: Thu, 28 Sep 2017 18:41:31 +0000 (-0700)
Subject: broadcom/vc5: Fix depth and stencil clear values.
X-Git-Tag: android-x86-8.1-r1~9177
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=7f3b8906979ba5f2c1876b4eb2c0b85314107511;p=android-x86%2Fexternal-mesa.git

broadcom/vc5: Fix depth and stencil clear values.

I had misread the packet description: We always have a 32f depth, and a
separate u8 stencil.
---

diff --git a/src/broadcom/cle/v3d_packet_v33.xml b/src/broadcom/cle/v3d_packet_v33.xml
index 82709c3cd63..bbfe0a991db 100644
--- a/src/broadcom/cle/v3d_packet_v33.xml
+++ b/src/broadcom/cle/v3d_packet_v33.xml
@@ -557,7 +557,7 @@
   <packet code="121" name="Tile Rendering Mode Configuration (Z Stencil Clear Values)" cl="R">
     <field name="unused" size="16" start="48" type="uint"/>
 
-    <field name="Z/S Clear Value" size="32" start="16" type="uint"/>
+    <field name="Z Clear Value" size="32" start="16" type="float"/>
 
     <field name="Stencil/VG Mask Clear Value" size="8" start="8" type="uint"/>
     <field name="sub-id" size="4" start="0" type="uint" default="3"/>
diff --git a/src/gallium/drivers/vc5/vc5_context.h b/src/gallium/drivers/vc5/vc5_context.h
index cac623adf26..472f0398596 100644
--- a/src/gallium/drivers/vc5/vc5_context.h
+++ b/src/gallium/drivers/vc5/vc5_context.h
@@ -245,7 +245,8 @@ struct vc5_job {
          */
         uint32_t resolve;
         uint32_t clear_color[2];
-        uint32_t clear_zs; /**< 24-bit unorm depth/stencil */
+        float clear_z;
+        uint8_t clear_s;
 
         /**
          * Set if some drawing (triangles, blits, or just a glClear()) has
diff --git a/src/gallium/drivers/vc5/vc5_draw.c b/src/gallium/drivers/vc5/vc5_draw.c
index 555e822a719..b7f8a7819f8 100644
--- a/src/gallium/drivers/vc5/vc5_draw.c
+++ b/src/gallium/drivers/vc5/vc5_draw.c
@@ -561,21 +561,15 @@ vc5_clear(struct pipe_context *pctx, unsigned buffers,
                 rsc->initialized_buffers |= (buffers & PIPE_CLEAR_COLOR0);
         }
 
-        if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
+        unsigned zsclear = buffers & PIPE_CLEAR_DEPTHSTENCIL;
+        if (zsclear) {
                 struct vc5_resource *rsc =
                         vc5_resource(vc5->framebuffer.zsbuf->texture);
-                unsigned zsclear = buffers & PIPE_CLEAR_DEPTHSTENCIL;
 
-                if (buffers & PIPE_CLEAR_DEPTH) {
-                        job->clear_zs |=
-                                util_pack_z_stencil(PIPE_FORMAT_S8_UINT_Z24_UNORM,
-                                                    depth, 0);
-                }
-                if (buffers & PIPE_CLEAR_STENCIL) {
-                        job->clear_zs |=
-                                util_pack_z_stencil(PIPE_FORMAT_S8_UINT_Z24_UNORM,
-                                                    0, stencil);
-                }
+                if (zsclear & PIPE_CLEAR_DEPTH)
+                        job->clear_z = depth;
+                if (zsclear & PIPE_CLEAR_STENCIL)
+                        job->clear_s = stencil;
 
                 rsc->initialized_buffers |= zsclear;
         }
diff --git a/src/gallium/drivers/vc5/vc5_rcl.c b/src/gallium/drivers/vc5/vc5_rcl.c
index e55a29772e0..ebc77dcce06 100644
--- a/src/gallium/drivers/vc5/vc5_rcl.c
+++ b/src/gallium/drivers/vc5/vc5_rcl.c
@@ -182,7 +182,8 @@ vc5_emit_rcl(struct vc5_job *job)
         /* Ends rendering mode config. */
         cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_Z_STENCIL_CLEAR_VALUES,
                 clear) {
-                clear.z_s_clear_value = job->clear_zs;
+                clear.z_clear_value = job->clear_z;
+                clear.stencil_vg_mask_clear_value = job->clear_s;
         };
 
         /* Always set initial block size before the first branch, which needs