From: Mitchel Humpherys <mitchelh@codeaurora.org>
Date: Tue, 17 May 2016 00:53:52 +0000 (-0700)
Subject: ARM: dts: msm: Fix interrupt type for a few IRQs
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=83822a290d8666d3b43d10f9cc0c97fedda839a6;p=sagit-ice-cold%2Fkernel_xiaomi_msm8998.git

ARM: dts: msm: Fix interrupt type for a few IRQs

The interrupt types for a few SMMU IRQs are incorrect.  Fix them.

CRs-Fixed: 1037068
Change-Id: Ic45e1ec592bf0503d456ad1029e32dfea5d63bf1
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
---

diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-cobalt.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-cobalt.dtsi
index 41af9b66d3c9..97abec77bed7 100644
--- a/arch/arm/boot/dts/qcom/msm-arm-smmu-cobalt.dtsi
+++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-cobalt.dtsi
@@ -23,16 +23,16 @@
 		qcom,register-save;
 		qcom,skip-init;
 		#global-interrupts = <2>;
-		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>;
 		clocks = <&clock_gcc clk_aggre1_noc_clk>;
 		clock-names = "smmu_aggre1_noc_clk";
 		#clock-cells = <1>;
@@ -46,28 +46,28 @@
 		qcom,register-save;
 		qcom,skip-init;
 		#global-interrupts = <2>;
-		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 353 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 358 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
 		clocks = <&clock_gcc clk_aggre2_noc_clk>;
 		clock-names = "smmu_aggre2_noc_clk";
 		#clock-cells = <1>;
@@ -164,14 +164,14 @@
 		qcom,register-save;
 		qcom,skip-init;
 		#global-interrupts = <2>;
-		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-			   <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
+			   <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>;
 		vdd-supply = <&gdsc_gpu_cx>;
 		clocks = <&clock_gcc clk_gcc_gpu_cfg_ahb_clk>,
 			<&clock_gcc clk_gcc_bimc_gfx_clk>,