From: Craig Topper <craig.topper@intel.com>
Date: Fri, 13 Oct 2017 00:18:58 +0000 (+0000)
Subject: [SelectionDAG] Correct the early out in SelectionDAG::getZeroExtendInReg to work... 
X-Git-Tag: android-x86-7.1-r4~9818
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=862291753bb9abe31b2dabbf52be4f24b2890e1c;p=android-x86%2Fexternal-llvm.git

[SelectionDAG] Correct the early out in SelectionDAG::getZeroExtendInReg to work properly for vector types.

I don't know if we ever hit this case or not. Turning it into an assert only fired on expanding some atomic operation in a SystemZ lit test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315648 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 744f5c5be2a..0d999984cdb 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1027,7 +1027,7 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) {
   assert(!VT.isVector() &&
          "getZeroExtendInReg should use the vector element type instead of "
          "the vector type!");
-  if (Op.getValueType() == VT) return Op;
+  if (Op.getValueType().getScalarType() == VT) return Op;
   unsigned BitWidth = Op.getScalarValueSizeInBits();
   APInt Imm = APInt::getLowBitsSet(BitWidth,
                                    VT.getSizeInBits());