From: Aleksandar Beserminji Date: Fri, 20 Oct 2017 14:35:41 +0000 (+0000) Subject: Revert "[mips] Reordering callseq* nodes to be linear" X-Git-Tag: android-x86-7.1-r4~9509 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=88f8f008102403a91a7fd5cab89991442f18033c;p=android-x86%2Fexternal-llvm.git Revert "[mips] Reordering callseq* nodes to be linear" This reverts commit r314507, because the original patch is causing test failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316215 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index d12da4bc32f..38b3c3fb160 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -2992,6 +2992,16 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, if (IsTailCall) ++NumTailCalls; + // Chain is the output chain of the last Load/Store or CopyToReg node. + // ByValChain is the output chain of the last Memcpy node created for copying + // byval arguments to the stack. + unsigned StackAlignment = TFL->getStackAlignment(); + NextStackOffset = alignTo(NextStackOffset, StackAlignment); + SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); + + if (!IsTailCall) + Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL); + SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, getPointerTy(DAG.getDataLayout())); @@ -3020,7 +3030,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, assert(ByValIdx < CCInfo.getInRegsParamsCount()); assert(!IsTailCall && "Do not tail-call optimize if there is a byval argument."); - Chain = passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, + passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), VA); CCInfo.nextInRegsParam(); @@ -3111,16 +3121,6 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, EVT Ty = Callee.getValueType(); bool GlobalOrExternal = false, IsCallReloc = false; - // Chain is the output chain of the last Load/Store or CopyToReg node. - // ByValChain is the output chain of the last Memcpy node created for copying - // byval arguments to the stack. - unsigned StackAlignment = TFL->getStackAlignment(); - NextStackOffset = alignTo(NextStackOffset, StackAlignment); - SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); - - if (!IsTailCall) - Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL); - // The long-calls feature is ignored in case of PIC. // While we do not support -mshared / -mno-shared properly, // ignore long-calls in case of -mabicalls too. @@ -4094,7 +4094,7 @@ void MipsTargetLowering::copyByValRegs( } // Copy byVal arg to registers and stack. -SDValue MipsTargetLowering::passByValArg( +void MipsTargetLowering::passByValArg( SDValue Chain, const SDLoc &DL, std::deque> &RegsToPass, SmallVectorImpl &MemOpChains, SDValue StackPtr, @@ -4127,7 +4127,7 @@ SDValue MipsTargetLowering::passByValArg( // Return if the struct has been fully copied. if (ByValSizeInBytes == OffsetInBytes) - return Chain; + return; // Copy the remainder of the byval argument with sub-word loads and shifts. if (LeftoverBytes) { @@ -4172,7 +4172,7 @@ SDValue MipsTargetLowering::passByValArg( unsigned ArgReg = ArgRegs[FirstReg + I]; RegsToPass.push_back(std::make_pair(ArgReg, Val)); - return Chain; + return; } } @@ -4182,13 +4182,12 @@ SDValue MipsTargetLowering::passByValArg( DAG.getConstant(OffsetInBytes, DL, PtrTy)); SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); - Chain = DAG.getMemcpy( - Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, DL, PtrTy), Alignment, - /*isVolatile=*/false, /*AlwaysInline=*/false, - /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo()); + Chain = DAG.getMemcpy(Chain, DL, Dst, Src, + DAG.getConstant(MemCpySize, DL, PtrTy), + Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, + /*isTailCall=*/false, + MachinePointerInfo(), MachinePointerInfo()); MemOpChains.push_back(Chain); - - return Chain; } void MipsTargetLowering::writeVarArgRegs(std::vector &OutChains, diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index b155332f786..4933cc1eb21 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -573,13 +573,13 @@ class TargetRegisterClass; MipsCCState &State) const; /// passByValArg - Pass a byval argument in registers or on stack. - SDValue passByValArg(SDValue Chain, const SDLoc &DL, - std::deque> &RegsToPass, - SmallVectorImpl &MemOpChains, - SDValue StackPtr, MachineFrameInfo &MFI, - SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, - unsigned LastReg, const ISD::ArgFlagsTy &Flags, - bool isLittle, const CCValAssign &VA) const; + void passByValArg(SDValue Chain, const SDLoc &DL, + std::deque> &RegsToPass, + SmallVectorImpl &MemOpChains, SDValue StackPtr, + MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, + unsigned FirstReg, unsigned LastReg, + const ISD::ArgFlagsTy &Flags, bool isLittle, + const CCValAssign &VA) const; /// writeVarArgRegs - Write variable function arguments passed in registers /// to the stack. Also create a stack frame object for the first variable diff --git a/test/CodeGen/Mips/largeimmprinting.ll b/test/CodeGen/Mips/largeimmprinting.ll index 2225fc78e52..f27e11425b9 100644 --- a/test/CodeGen/Mips/largeimmprinting.ll +++ b/test/CodeGen/Mips/largeimmprinting.ll @@ -1,9 +1,8 @@ -; RUN: llc -march=mipsel -relocation-model=pic -verify-machineinstrs < %s | \ -; RUN: FileCheck %s -check-prefix=32 -; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic \ -; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=64 -; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic \ -; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=64 +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=32 +; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefix=64 +; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefix=64 %struct.S1 = type { [65536 x i8] } diff --git a/test/CodeGen/Mips/llvm-ir/mul.ll b/test/CodeGen/Mips/llvm-ir/mul.ll index e32aa646c04..1562372ce9a 100644 --- a/test/CodeGen/Mips/llvm-ir/mul.ll +++ b/test/CodeGen/Mips/llvm-ir/mul.ll @@ -268,7 +268,7 @@ entry: ; MM64R6: daddu $2, $[[T1]], $[[T0]] ; MM64R6-DAG: dmul $3, $5, $7 - ; MM32: lw $25, %call16(__multi3) + ; MM32: lw $25, %call16(__multi3)($16) %r = mul i128 %a, %b ret i128 %r diff --git a/test/CodeGen/Mips/llvm-ir/sdiv.ll b/test/CodeGen/Mips/llvm-ir/sdiv.ll index 087b28b3acd..defd25bb41a 100644 --- a/test/CodeGen/Mips/llvm-ir/sdiv.ll +++ b/test/CodeGen/Mips/llvm-ir/sdiv.ll @@ -190,7 +190,7 @@ entry: ; GP64-NOT-R6: ld $25, %call16(__divti3)($gp) ; 64R6: ld $25, %call16(__divti3)($gp) - ; MM32: lw $25, %call16(__divti3) + ; MM32: lw $25, %call16(__divti3)($16) ; MM64: ld $25, %call16(__divti3)($2) diff --git a/test/CodeGen/Mips/llvm-ir/srem.ll b/test/CodeGen/Mips/llvm-ir/srem.ll index 7466e5679bb..42664d7457e 100644 --- a/test/CodeGen/Mips/llvm-ir/srem.ll +++ b/test/CodeGen/Mips/llvm-ir/srem.ll @@ -182,7 +182,7 @@ entry: ; GP64-NOT-R6: ld $25, %call16(__modti3)($gp) ; 64R6: ld $25, %call16(__modti3)($gp) - ; MM32: lw $25, %call16(__modti3) + ; MM32: lw $25, %call16(__modti3)($16) ; MM64: ld $25, %call16(__modti3)($2) diff --git a/test/CodeGen/Mips/llvm-ir/udiv.ll b/test/CodeGen/Mips/llvm-ir/udiv.ll index 122d1385353..78ab36442a9 100644 --- a/test/CodeGen/Mips/llvm-ir/udiv.ll +++ b/test/CodeGen/Mips/llvm-ir/udiv.ll @@ -152,7 +152,7 @@ entry: ; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp) ; 64-R6: ld $25, %call16(__udivti3)($gp) - ; MM32: lw $25, %call16(__udivti3) + ; MM32: lw $25, %call16(__udivti3)($16) ; MM64: ld $25, %call16(__udivti3)($2) diff --git a/test/CodeGen/Mips/llvm-ir/urem.ll b/test/CodeGen/Mips/llvm-ir/urem.ll index 7fd3d79f843..160c126c7e3 100644 --- a/test/CodeGen/Mips/llvm-ir/urem.ll +++ b/test/CodeGen/Mips/llvm-ir/urem.ll @@ -208,7 +208,7 @@ entry: ; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp) ; 64R6: ld $25, %call16(__umodti3)($gp) - ; MM32: lw $25, %call16(__umodti3) + ; MM32: lw $25, %call16(__umodti3)($16) ; MM64: ld $25, %call16(__umodti3)($2)