From: Mark Searles <m.c.searles@gmail.com>
Date: Tue, 12 Jun 2018 00:41:26 +0000 (+0000)
Subject: [AMDGPU] prevent hitting Assertion `isReg() && "Wrong MachineOperand accessor"'
X-Git-Tag: android-x86-8.1-r1~2249
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=8f93b43810b56256d63a1dc7856b8d09aa8cad88;p=android-x86%2Fexternal-llvm.git

[AMDGPU] prevent hitting Assertion `isReg() && "Wrong MachineOperand accessor"'

The use iterator, used within findMaskOperands(), can return anything which is
not a def. isUse() requires a register, so check isReg() before calling isUse().

Differential Revision: https://reviews.llvm.org/D48047

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334459 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/SILowerControlFlow.cpp b/lib/Target/AMDGPU/SILowerControlFlow.cpp
index a8426c3039f..3c0c5f93ce9 100644
--- a/lib/Target/AMDGPU/SILowerControlFlow.cpp
+++ b/lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -453,8 +453,8 @@ void SILowerControlFlow::findMaskOperands(MachineInstr &MI, unsigned OpNo,
       return;
 
   for (const auto &SrcOp : Def->explicit_operands())
-    if (SrcOp.isUse() && (!SrcOp.isReg() ||
-        TargetRegisterInfo::isVirtualRegister(SrcOp.getReg()) ||
+    if (SrcOp.isReg() && SrcOp.isUse() &&
+        (TargetRegisterInfo::isVirtualRegister(SrcOp.getReg()) ||
         SrcOp.getReg() == AMDGPU::EXEC))
       Src.push_back(SrcOp);
 }
diff --git a/test/CodeGen/AMDGPU/si-lower-control-flow.mir b/test/CodeGen/AMDGPU/si-lower-control-flow.mir
new file mode 100644
index 00000000000..7513e8f02d4
--- /dev/null
+++ b/test/CodeGen/AMDGPU/si-lower-control-flow.mir
@@ -0,0 +1,23 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgizcl -run-pass=si-lower-control-flow -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN %s
+
+# Check that assert is not triggered
+# GCN-LABEL: name: si-lower-control-flow{{$}}
+# GCN-CHECK: S_LOAD_DWORD_IMM
+
+--- |
+
+  define amdgpu_kernel void @si-lower-control-flow() {
+    ret void
+  }
+
+...
+---
+name: si-lower-control-flow
+body: |
+  bb.0:
+    %0:sgpr_64 = COPY $sgpr4_sgpr5
+    %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 16, 0
+    %2:sreg_32_xm0 = S_AND_B32 %1, 255, implicit-def $scc
+    %3:sreg_32_xm0 = S_AND_B32 65535, %2, implicit-def $scc
+    S_ENDPGM
+...