From: Thiemo Seufer Date: Tue, 29 Aug 2006 12:38:45 +0000 (+0000) Subject: * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=91fdae5f6fb5a3d72df80fab89c0db125f8f0eb9;p=pf3gnuchains%2Fpf3gnuchains3x.git * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and mips3264r2.igen. Add missing dependency rules. * m16e.igen: Support for mips16e save/restore instructions. --- diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 6ea29d6d71..f48219a591 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,10 @@ +2006-08-29 Thiemo Seufer + David Ung + + * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and + mips3264r2.igen. Add missing dependency rules. + * m16e.igen: Support for mips16e save/restore instructions. + 2006-06-13 Richard Earnshaw * configure: Regenerated. diff --git a/sim/mips/Makefile.in b/sim/mips/Makefile.in index 9c3e838d0a..817dcdf80b 100644 --- a/sim/mips/Makefile.in +++ b/sim/mips/Makefile.in @@ -92,12 +92,14 @@ IGEN_DC=$(srcdir)/mips.dc M16_DC=$(srcdir)/m16.dc IGEN_INCLUDE=\ $(srcdir)/m16.igen \ + $(srcdir)/m16e.igen \ $(srcdir)/mdmx.igen \ $(srcdir)/mips3d.igen \ $(srcdir)/sb1.igen \ $(srcdir)/tx.igen \ $(srcdir)/vr.igen \ $(srcdir)/dsp.igen \ + $(srcdir)/mips3264r2.igen \ # NB: Since these can be built by a number of generators, care # must be taken to ensure that they are only dependant on @@ -184,8 +186,15 @@ support.o: sim-main.h support.c $(SIM_EXTRA_DEPS) idecode.o: sim-main.h idecode.c $(SIM_EXTRA_DEPS) itable.o: sim-main.h itable.c $(SIM_EXTRA_DEPS) +m16_semantics.o: sim-main.h m16_semantics.c $(SIM_EXTRA_DEPS) +m16_support.o: sim-main.h m16_support.c $(SIM_EXTRA_DEPS) +m16_idecode.o: sim-main.h m16_idecode.c $(SIM_EXTRA_DEPS) +m16_icache.o: sim-main.h m16_icache.c $(SIM_EXTRA_DEPS) - +m32_semantics.o: sim-main.h m32_semantics.c $(SIM_EXTRA_DEPS) +m32_support.o: sim-main.h m32_support.c $(SIM_EXTRA_DEPS) +m32_idecode.o: sim-main.h m32_idecode.c $(SIM_EXTRA_DEPS) +m32_icache.o: sim-main.h m32_icache.c $(SIM_EXTRA_DEPS) BUILT_SRC_FROM_M16 = \ m16_icache.h \ diff --git a/sim/mips/m16e.igen b/sim/mips/m16e.igen index 2d7a073604..8808906175 100644 --- a/sim/mips/m16e.igen +++ b/sim/mips/m16e.igen @@ -103,3 +103,267 @@ RA = NIA; NIA = GPR[TRX]; } + + +// format routines for save/restore +:%s::::RAS:int ras +*mips16e +{ + static char buf[10]; + buf[0] = '\0'; + if (ras & 4) + strcat (buf,"ra,"); + if (ras & 2) + strcat (buf,"s0,"); + if (ras & 1) + strcat (buf,"s1,"); + return (buf); +} + +:%s::::XSREGS:int xsregs +*mips16e +{ + if (xsregs > 6) + return "s2,s3,s4,s5,s6,s7,s8,"; + if (xsregs > 5) + return "s2,s3,s4,s5,s6,s7,"; + if (xsregs > 4) + return "s2,s3,s4,s5,s6,"; + if (xsregs > 3) + return "s2,s3,s4,s5,"; + if (xsregs > 2) + return "s2,s3,s4,"; + if (xsregs > 1) + return "s2,s3,"; + if (xsregs > 0) + return "s2,"; + return ""; +} + +:%s::::AREGS:int aregs +*mips16e +{ + // Fixme: how is the arg/static distinction made by the assembler? + static const char * const aregstr[16] = { + "", + "A3,", + "A2,A3,", + "A1,A2,A3,", + "A0,A1,A2,A3,", + "a0,", + "a0,A3,", + "a0,A2,A3,", + "a0,A1,A2,A3,", + "a0,a1,", + "a0,a1,A3,", + "a0,a1,A2,A3,", + "a0,a1,a2,", + "a0,a1,a2,A3,", + "?," + }; + return aregstr[aregs]; +} + +:compute:::int:SFRAME:FS:((FS == 0) ? 128 \: (FS << 3)) +:compute:::int:BFRAME:FSHI,FSLO:(((FSHI << 4) | FSLO) << 3) + +:function:::void:do_save:int xsregs, int aregs, int ras0s1, int framesize +{ + unsigned_word temp; + int args, astatic; + + temp = GPR[29]; + + /* writes are in the same order as the hardware description... */ + switch (aregs) { + case 0: case 1: case 2: case 3: case 11: + args = 0; + break; + case 4: case 5: case 6: case 7: + args = 1; + break; + case 8: case 9: case 10: + args = 2; + break; + case 12: case 13: + args = 3; + break; + case 14: + args = 4; + break; + default: + sim_engine_abort (SD, CPU, CIA, "save: aregs=%d causes unpredictable results\n", aregs); + } + if (args > 0) { + do_store (SD_, AccessLength_WORD, temp, 0, GPR[4]); + if (args > 1) { + do_store (SD_,AccessLength_WORD, temp, 4 , GPR[5]); + if (args > 2) { + do_store (SD_,AccessLength_WORD, temp, 8 , GPR[6]); + if (args > 3) { + do_store (SD_,AccessLength_WORD, temp, 12, GPR[7]); + } + } + } + } + + if (ras0s1 & 4) + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[31]); + + switch (xsregs) { + case 7: + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[30]); + case 6: + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[23]); + case 5: + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[22]); + case 4: + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[21]); + case 3: + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[20]); + case 2: + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[19]); + case 1: + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[18]); + } + + if (ras0s1 & 1) + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[17]); + if (ras0s1 & 2) + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[16]); + + switch (aregs) { + case 0: case 4: case 8: case 12: case 14: + astatic = 0; + break; + case 1: case 5: case 9: case 13: + astatic = 1; + break; + case 2: case 6: case 10: + astatic = 2; + break; + case 3: case 7: + astatic = 3; + break; + case 11: + astatic = 4; + break; + default: + sim_engine_abort (SD, CPU, CIA, "save: aregs=%d causes unpredictable results\n", aregs); + } + if (astatic > 0) { + do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[7]); + if (astatic > 1) { + do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[6]); + if (astatic > 2) { + do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[5]); + if (astatic > 3) { + do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[4]); + } + } + } + } + + GPR[29] -= framesize; +} + +01100,100,1,3.RAS,4.FS:I8:16::SAVE +"save %s," +*mips16e +{ + do_save (SD_, 0, 0, RAS, SFRAME); +} + + +11110,3.XSREGS,4.FSHI,4.AREGS + 01100,100,1,3.RAS,4.FSLO:EXT-I8:16::SAVE +"save %s%s%s" +*mips16e +{ + do_save (SD_, XSREGS, AREGS, RAS, BFRAME); +} + + +:function:::void:do_restore:int xsregs, int aregs, int ras0s1, int framesize +*mips16e +{ + unsigned_word temp, temp2; + int astatic; + + temp = GPR[29] + framesize; + temp2 = temp; + + /* reads are in the same order as the hardware description... */ + + if (ras0s1 & 4) + GPR[31] = EXTEND32 (do_load(SD_, AccessLength_WORD, temp -= 4, 0)); + + switch (xsregs) { + case 7: + GPR[30] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + case 6: + GPR[23] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + case 5: + GPR[22] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + case 4: + GPR[21] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + case 3: + GPR[20] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + case 2: + GPR[19] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + case 1: + GPR[18] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + } + + if (ras0s1 & 1) + GPR[17] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + if (ras0s1 & 2) + GPR[16] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + + switch (aregs) { + case 0: case 4: case 8: case 12: case 14: + astatic = 0; + break; + case 1: case 5: case 9: case 13: + astatic = 1; + break; + case 2: case 6: case 10: + astatic = 2; + break; + case 3: case 7: + astatic = 3; + break; + case 11: + astatic = 4; + break; + default: + sim_engine_abort (SD, CPU, CIA, "save: aregs=%d causes unpredictable results\n", aregs); + } + if (astatic > 0) { + GPR[7] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + if (astatic > 1) { + GPR[6] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + if (astatic > 2) { + GPR[5] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + if (astatic > 3) { + GPR[4] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + } + } + } + } + + GPR[29] = temp2; +} + +01100,100,0,3.RAS,4.FS:I8:16::RESTORE +"restore %s," +*mips16e +{ + do_restore (SD_,0,0,RAS,SFRAME); +} + +11110,3.XSREGS,4.FSHI,4.AREGS + 01100,100,0,3.RAS,4.FSLO:EXT-I8:16::RESTORE +"restore %s%s%s" +*mips16e +{ + do_restore (SD_,XSREGS,AREGS,RAS,BFRAME); +}