From: Eric Christopher Date: Thu, 30 Mar 2017 22:34:20 +0000 (+0000) Subject: getPristineRegs is not accurately considering shrink wrapping puts X-Git-Tag: android-x86-7.1-r4~18317 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=95604f98b90d55fb5f1605460393a7e466d4ac13;p=android-x86%2Fexternal-llvm.git getPristineRegs is not accurately considering shrink wrapping puts registers not saved in certain blocks. Use explicit getCalleeSavedInfo and isLiveIn instead. This fixes pr32292. Patch by Tim Shen! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299124 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/AsmParser/LLParser.cpp b/lib/AsmParser/LLParser.cpp index ab315dd2c7f..d8f6c1c5146 100644 --- a/lib/AsmParser/LLParser.cpp +++ b/lib/AsmParser/LLParser.cpp @@ -4593,6 +4593,9 @@ bool LLParser::parseConstantValue(Type *Ty, Constant *&C) { C = cast(V); return false; } + case ValID::t_Null: + C = Constant::getNullValue(Ty); + return false; default: return Error(Loc, "expected a constant value"); } diff --git a/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/lib/CodeGen/AggressiveAntiDepBreaker.cpp index a60a43a2ddc..955524c2a67 100644 --- a/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ b/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -166,7 +166,8 @@ void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) { for (const MCPhysReg *I = MF.getRegInfo().getCalleeSavedRegs(); *I; ++I) { unsigned Reg = *I; - if (!IsReturnBlock && !Pristine.test(Reg)) continue; + if (!IsReturnBlock && !(Pristine.test(Reg) || BB->isLiveIn(Reg))) + continue; for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { unsigned AliasReg = *AI; State->UnionGroups(AliasReg, 0); diff --git a/lib/CodeGen/CriticalAntiDepBreaker.cpp b/lib/CodeGen/CriticalAntiDepBreaker.cpp index 615d7eb7b4d..e1eeddf0816 100644 --- a/lib/CodeGen/CriticalAntiDepBreaker.cpp +++ b/lib/CodeGen/CriticalAntiDepBreaker.cpp @@ -73,7 +73,9 @@ void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) { BitVector Pristine = MFI.getPristineRegs(MF); for (const MCPhysReg *I = MF.getRegInfo().getCalleeSavedRegs(); *I; ++I) { - if (!IsReturnBlock && !Pristine.test(*I)) continue; + unsigned Reg = *I; + if (!IsReturnBlock && !(Pristine.test(Reg) || BB->isLiveIn(Reg))) + continue; for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { unsigned Reg = *AI; Classes[Reg] = reinterpret_cast(-1);