From: Richard Henderson Date: Sat, 14 Jan 2023 18:06:01 +0000 (-1000) Subject: target/i386: Fix C flag for BLSI, BLSMSK, BLSR X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=99282098dc74c2055bde5652bde6cf0067d0c370;p=qmiga%2Fqemu.git target/i386: Fix C flag for BLSI, BLSMSK, BLSR We forgot to set cc_src, which is used for computing C. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1370 Signed-off-by: Richard Henderson Message-Id: <20230114180601.2993644-1-richard.henderson@linaro.org> Cc: qemu-stable@nongnu.org Fixes: 1d0b926150e5 ("target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder", 2022-10-18) Signed-off-by: Paolo Bonzini --- diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 99f6ba6e19..4d7702c106 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1111,6 +1111,7 @@ static void gen_BLSI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) { MemOp ot = decode->op[0].ot; + tcg_gen_mov_tl(cpu_cc_src, s->T0); tcg_gen_neg_tl(s->T1, s->T0); tcg_gen_and_tl(s->T0, s->T0, s->T1); tcg_gen_mov_tl(cpu_cc_dst, s->T0); @@ -1121,6 +1122,7 @@ static void gen_BLSMSK(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode { MemOp ot = decode->op[0].ot; + tcg_gen_mov_tl(cpu_cc_src, s->T0); tcg_gen_subi_tl(s->T1, s->T0, 1); tcg_gen_xor_tl(s->T0, s->T0, s->T1); tcg_gen_mov_tl(cpu_cc_dst, s->T0); @@ -1131,6 +1133,7 @@ static void gen_BLSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) { MemOp ot = decode->op[0].ot; + tcg_gen_mov_tl(cpu_cc_src, s->T0); tcg_gen_subi_tl(s->T1, s->T0, 1); tcg_gen_and_tl(s->T0, s->T0, s->T1); tcg_gen_mov_tl(cpu_cc_dst, s->T0);