From: malc <malc@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Mon, 23 Jun 2008 05:47:03 +0000 (+0000)
Subject: Shuffle contents of tcg_target_reg_alloc_order
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=a35e86c55fa2858c7828058f2e59956597aaa7af;p=qmiga%2Fqemu.git

Shuffle contents of tcg_target_reg_alloc_order

Move reserved/volatile registers down. Currently qemu_ld/stXX are
marked with TCG_OPF_CALL_CLOBBER and since memory accesses are
frequent and R3 through R12 are volatile moving this down results in
less spills and tighter generated code.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4778 c046a42c-6fe2-441c-8c8c-71466251a162
---

diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index c829b642c6..8d5f7dcfce 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -67,9 +67,20 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
 };
 
 static const int tcg_target_reg_alloc_order[] = {
-    TCG_REG_R0,
-    TCG_REG_R1,
-    TCG_REG_R2,
+    TCG_REG_R14,
+    TCG_REG_R15,
+    TCG_REG_R16,
+    TCG_REG_R17,
+    TCG_REG_R18,
+    TCG_REG_R19,
+    TCG_REG_R20,
+    TCG_REG_R21,
+    TCG_REG_R22,
+    TCG_REG_R23,
+    TCG_REG_R28,
+    TCG_REG_R29,
+    TCG_REG_R30,
+    TCG_REG_R31,
     TCG_REG_R3,
     TCG_REG_R4,
     TCG_REG_R5,
@@ -81,24 +92,13 @@ static const int tcg_target_reg_alloc_order[] = {
     TCG_REG_R11,
     TCG_REG_R12,
     TCG_REG_R13,
-    TCG_REG_R14,
-    TCG_REG_R15,
-    TCG_REG_R16,
-    TCG_REG_R17,
-    TCG_REG_R18,
-    TCG_REG_R19,
-    TCG_REG_R20,
-    TCG_REG_R21,
-    TCG_REG_R22,
-    TCG_REG_R23,
+    TCG_REG_R0,
+    TCG_REG_R1,
+    TCG_REG_R2,
     TCG_REG_R24,
     TCG_REG_R25,
     TCG_REG_R26,
-    TCG_REG_R27,
-    TCG_REG_R28,
-    TCG_REG_R29,
-    TCG_REG_R30,
-    TCG_REG_R31
+    TCG_REG_R27
 };
 
 static const int tcg_target_call_iarg_regs[] = {