From: Rich Felker <dalias@aerifal.cx>
Date: Sat, 18 Apr 2015 02:19:01 +0000 (-0400)
Subject: fix PLT call offset in sh dlsym asm
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=aecdbb3042704075b303b626da424aa0665e4f97;p=android-x86%2Fexternal-musl-libc.git

fix PLT call offset in sh dlsym asm

the braf instruction's destination register is an offset from the
address of the braf instruction plus 4 (or equivalently, the address
of the next instruction after the delay slot). the code for dlsym was
incorrectly computing the offset to pass using the address of the
delay slot itself. in other places, a label was placed after the delay
slot, but I find this confusing. putting the label on the branch
instruction itself, and manually adding 4, makes it more clear which
branch the offset in the constant pool goes with.
---

diff --git a/src/ldso/sh/dlsym.s b/src/ldso/sh/dlsym.s
index bc8fd679..11a6fff5 100644
--- a/src/ldso/sh/dlsym.s
+++ b/src/ldso/sh/dlsym.s
@@ -4,8 +4,8 @@
 .type   dlsym, @function
 dlsym:
 	mov.l L1, r0
-	braf  r0
-1:	 mov.l @r15, r6
+1:	braf  r0
+	 mov.l @r15, r6
 
 .align 2
-L1:	.long __dlsym@PLT-(1b-.)
+L1:	.long __dlsym@PLT-(1b+4-.)