From: Sanjay Patel <spatel@rotateright.com>
Date: Wed, 30 Nov 2016 20:20:49 +0000 (+0000)
Subject: [InstCombine] add tests to show potentially missed logic+trunc transforms; NFC
X-Git-Tag: android-x86-7.1-r4~23880
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=ba32f788d84500178e79b15c3b93e4f94a49d72a;p=android-x86%2Fexternal-llvm.git

[InstCombine] add tests to show potentially missed logic+trunc transforms; NFC


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288270 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/Transforms/InstCombine/narrow.ll b/test/Transforms/InstCombine/narrow.ll
index 7416568f586..d51164875ef 100644
--- a/test/Transforms/InstCombine/narrow.ll
+++ b/test/Transforms/InstCombine/narrow.ll
@@ -1,7 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
-; Eliminating the casts in this testcase (by narrowing the AND operation) 
+target datalayout = "n8:16:32:64"
+
+; Eliminating the casts in this testcase (by narrowing the AND operation)
 ; allows instcombine to realize the function always returns false.
 
 define i1 @test1(i32 %A, i32 %B) {
@@ -17,3 +19,81 @@ define i1 @test1(i32 %A, i32 %B) {
   ret i1 %ELIM3
 }
 
+; TODO: The next 6 (3 logic ops * (scalar+vector)) tests show potential cases for narrowing a bitwise logic op.
+
+define i32 @shrink_xor(i64 %a) {
+; CHECK-LABEL: @shrink_xor(
+; CHECK-NEXT:    [[XOR:%.*]] = xor i64 %a, 1
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc i64 [[XOR]] to i32
+; CHECK-NEXT:    ret i32 [[TRUNC]]
+;
+  %xor = xor i64 %a, 1
+  %trunc = trunc i64 %xor to i32
+  ret i32 %trunc
+}
+
+; Vectors (with splat constants) should get the same transform.
+
+define <2 x i32> @shrink_xor_vec(<2 x i64> %a) {
+; CHECK-LABEL: @shrink_xor_vec(
+; CHECK-NEXT:    [[XOR:%.*]] = xor <2 x i64> %a, <i64 2, i64 2>
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc <2 x i64> [[XOR]] to <2 x i32>
+; CHECK-NEXT:    ret <2 x i32> [[TRUNC]]
+;
+  %xor = xor <2 x i64> %a, <i64 2, i64 2>
+  %trunc = trunc <2 x i64> %xor to <2 x i32>
+  ret <2 x i32> %trunc
+}
+
+; Source and dest types are not in the datalayout.
+
+define i3 @shrink_or(i6 %a) {
+; CHECK-LABEL: @shrink_or(
+; CHECK-NEXT:    [[OR:%.*]] = or i6 %a, 1
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc i6 [[OR]] to i3
+; CHECK-NEXT:    ret i3 [[TRUNC]]
+;
+  %or = or i6 %a, 33
+  %trunc = trunc i6 %or to i3
+  ret i3 %trunc
+}
+
+; Vectors (with non-splat constants) should get the same transform.
+
+define <2 x i8> @shrink_or_vec(<2 x i16> %a) {
+; CHECK-LABEL: @shrink_or_vec(
+; CHECK-NEXT:    [[OR:%.*]] = or <2 x i16> %a, <i16 -1, i16 256>
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc <2 x i16> [[OR]] to <2 x i8>
+; CHECK-NEXT:    ret <2 x i8> [[TRUNC]]
+;
+  %or = or <2 x i16> %a, <i16 -1, i16 256>
+  %trunc = trunc <2 x i16> %or to <2 x i8>
+  ret <2 x i8> %trunc
+}
+
+; We discriminate against weird types?
+
+define i31 @shrink_and(i64 %a) {
+; CHECK-LABEL: @shrink_and(
+; CHECK-NEXT:    [[AND:%.*]] = and i64 %a, 42
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc i64 [[AND]] to i31
+; CHECK-NEXT:    ret i31 [[TRUNC]]
+;
+  %and = and i64 %a, 42
+  %trunc = trunc i64 %and to i31
+  ret i31 %trunc
+}
+
+; Chop the top of the constant(s) if needed.
+
+define <2 x i32> @shrink_and_vec(<2 x i33> %a) {
+; CHECK-LABEL: @shrink_and_vec(
+; CHECK-NEXT:    [[AND:%.*]] = and <2 x i33> %a, <i33 -4294967296, i33 6>
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc <2 x i33> [[AND]] to <2 x i32>
+; CHECK-NEXT:    ret <2 x i32> [[TRUNC]]
+;
+  %and = and <2 x i33> %a, <i33 4294967296, i33 6>
+  %trunc = trunc <2 x i33> %and to <2 x i32>
+  ret <2 x i32> %trunc
+}
+