From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Sun, 10 Dec 2017 12:43:53 +0000 (+0000)
Subject: [X86] Flag ZNVER1 scheduler model as complete
X-Git-Tag: android-x86-7.1-r4~7476
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=bb436139d26bad07b2fe3fff1fab8ba36f5fca84;p=android-x86%2Fexternal-llvm.git

[X86] Flag ZNVER1 scheduler model as complete

We just have to locally tag COPY as WriteMove

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320304 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ScheduleZnver1.td b/lib/Target/X86/X86ScheduleZnver1.td
index 2bae818cfcd..872577787ac 100644
--- a/lib/Target/X86/X86ScheduleZnver1.td
+++ b/lib/Target/X86/X86ScheduleZnver1.td
@@ -21,12 +21,6 @@ def Znver1Model : SchedMachineModel {
   let MispredictPenalty = 17;
   let HighLatency = 25;
   let PostRAScheduler = 1;
-
-  // FIXME: This variable is required for incomplete model.
-  // We haven't catered all instructions.
-  // So, we reset the value of this variable so as to
-  // say that the model is incomplete.
-  let CompleteModel = 0;
 }
 
 let SchedModel = Znver1Model in {
@@ -140,6 +134,9 @@ defm : ZnWriteResPair<WriteALU,   ZnALU, 1>;
 defm : ZnWriteResPair<WriteShift, ZnALU, 1>;
 defm : ZnWriteResPair<WriteJump,  ZnALU, 1>;
 
+// Treat misc copies as a move.
+def : InstRW<[WriteMove], (instrs COPY)>;
+
 // IDIV
 def : WriteRes<WriteIDiv, [ZnALU2, ZnDivider]> {
   let Latency = 41;