From: Tim Northover Date: Sat, 22 Sep 2012 11:18:19 +0000 (+0000) Subject: Fix edge cases of ARM shift operands in arith instructions. X-Git-Tag: android-x86-6.0-r1~179^2~3041 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=bb5174246b5d0dfbd057b3641f5e134fe74ea0f4;p=android-x86%2Fexternal-llvm.git Fix edge cases of ARM shift operands in arith instructions. As before with load instructions, oddities like "asr #32", "rrx" could be printed incorrectly. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164456 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp index 60f92f82d40..88798716cd1 100644 --- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -302,11 +302,8 @@ void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum, O << getRegisterName(MO1.getReg()); // Print the shift opc. - ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm()); - O << ", " << ARM_AM::getShiftOpcStr(ShOpc); - if (ShOpc == ARM_AM::rrx) - return; - O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); + printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), + ARM_AM::getSORegOffset(MO2.getImm())); } @@ -340,31 +337,6 @@ void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, O << "]"; } -void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(Op); - const MCOperand &MO2 = MI->getOperand(Op+1); - const MCOperand &MO3 = MI->getOperand(Op+2); - - O << "[" << getRegisterName(MO1.getReg()) << "], "; - - if (!MO2.getReg()) { - unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm()); - O << '#' - << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())) - << ImmOffs; - return; - } - - O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())) - << getRegisterName(MO2.getReg()); - - if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) - O << ", " - << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm())) - << " #" << ShImm; -} - void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op, raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(Op); @@ -392,11 +364,9 @@ void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op, const MCOperand &MO3 = MI->getOperand(Op+2); unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm()); + assert(IdxMode != ARMII::IndexModePost && + "Should be pre or offset index op"); - if (IdxMode == ARMII::IndexModePost) { - printAM2PostIndexOp(MI, Op, O); - return; - } printAM2PreOrOffsetIndexOp(MI, Op, O); } @@ -922,10 +892,8 @@ void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum, // Print the shift opc. assert(MO2.isImm() && "Not a valid t2_so_reg value!"); - ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm()); - O << ", " << ARM_AM::getShiftOpcStr(ShOpc); - if (ShOpc != ARM_AM::rrx) - O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); + printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), + ARM_AM::getSORegOffset(MO2.getImm())); } void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, diff --git a/test/MC/ARM/arm-shift-encoding.s b/test/MC/ARM/arm-shift-encoding.s index c849380ff2b..3c57b67f6e3 100644 --- a/test/MC/ARM/arm-shift-encoding.s +++ b/test/MC/ARM/arm-shift-encoding.s @@ -74,3 +74,46 @@ @ CHECK: ldr r3, [r4], r5 @ encoding: [0x05,0x30,0x94,0xe6] @ CHECK: str r6, [r7], r8 @ encoding: [0x08,0x60,0x87,0xe6] @ CHECK: str r9, [r10], r11 @ encoding: [0x0b,0x90,0x8a,0xe6] + +@ Uses printSORegImmOperand(), used by ADCrsi ADDrsi ANDrsi BICrsi EORrsi +@ ORRrsi RSBrsi RSCrsi SBCrsi SUBrsi CMNzrsi CMPrsi MOVsi MVNsi TEQrsi TSTrsi + + adc sp, lr, pc + adc r1, r8, r9, lsr #32 + adc r2, r7, pc, lsr #16 + adc r3, r6, r10, lsl #0 + adc r4, r5, lr, lsl #16 + adc r5, r4, r11, asr #32 + adc r6, r3, sp, asr #16 + adc r7, r2, r12, rrx + adc r8, r1, r0, ror #16 + +@ CHECK: adc sp, lr, pc @ encoding: [0x0f,0xd0,0xae,0xe0] +@ CHECK: adc r1, r8, r9, lsr #32 @ encoding: [0x29,0x10,0xa8,0xe0] +@ CHECK: adc r2, r7, pc, lsr #16 @ encoding: [0x2f,0x28,0xa7,0xe0] +@ CHECK: adc r3, r6, r10 @ encoding: [0x0a,0x30,0xa6,0xe0] +@ CHECK: adc r4, r5, lr, lsl #16 @ encoding: [0x0e,0x48,0xa5,0xe0] +@ CHECK: adc r5, r4, r11, asr #32 @ encoding: [0x4b,0x50,0xa4,0xe0] +@ CHECK: adc r6, r3, sp, asr #16 @ encoding: [0x4d,0x68,0xa3,0xe0] +@ CHECK: adc r7, r2, r12, rrx @ encoding: [0x6c,0x70,0xa2,0xe0] +@ CHECK: adc r8, r1, r0, ror #16 @ encoding: [0x60,0x88,0xa1,0xe0] + + cmp sp, lr + cmp r1, r8, lsr #32 + cmp r2, r7, lsr #16 + cmp r3, r6, lsl #0 + cmp r4, r5, lsl #16 + cmp r5, r4, asr #32 + cmp r6, r3, asr #16 + cmp r7, r2, rrx + cmp r8, r1, ror #16 + +@ CHECK: cmp sp, lr @ encoding: [0x0e,0x00,0x5d,0xe1] +@ CHECK: cmp r1, r8, lsr #32 @ encoding: [0x28,0x00,0x51,0xe1] +@ CHECK: cmp r2, r7, lsr #16 @ encoding: [0x27,0x08,0x52,0xe1] +@ CHECK: cmp r3, r6 @ encoding: [0x06,0x00,0x53,0xe1] +@ CHECK: cmp r4, r5, lsl #16 @ encoding: [0x05,0x08,0x54,0xe1] +@ CHECK: cmp r5, r4, asr #32 @ encoding: [0x44,0x00,0x55,0xe1] +@ CHECK: cmp r6, r3, asr #16 @ encoding: [0x43,0x08,0x56,0xe1] +@ CHECK: cmp r7, r2, rrx @ encoding: [0x62,0x00,0x57,0xe1] +@ CHECK: cmp r8, r1, ror #16 @ encoding: [0x61,0x08,0x58,0xe1] diff --git a/test/MC/ARM/thumb-shift-encoding.s b/test/MC/ARM/thumb-shift-encoding.s new file mode 100644 index 00000000000..54284132b65 --- /dev/null +++ b/test/MC/ARM/thumb-shift-encoding.s @@ -0,0 +1,45 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumbv7 -show-encoding < %s | FileCheck %s + +@ Uses printT2SOOperand(), used by t2ADCrs t2ADDrs t2ANDrs t2BICrs t2EORrs +@ t2ORNrs t2ORRrs t2RSBrs t2SBCrs t2SUBrs t2CMNzrs t2CMPrs t2MOVSsi t2MOVsi +@ t2MVNs t2TEQrs t2TSTrs + + sbc.w r12, lr, r0 + sbc.w r1, r8, r9, lsr #32 + sbc.w r2, r7, pc, lsr #16 + sbc.w r3, r6, r10, lsl #0 + sbc.w r4, r5, lr, lsl #16 + sbc.w r5, r4, r11, asr #32 + sbc.w r6, r3, sp, asr #16 + sbc.w r7, r2, r12, rrx + sbc.w r8, r1, r0, ror #16 + +@ CHECK: sbc.w r12, lr, r0 @ encoding: [0x6e,0xeb,0x00,0x0c] +@ CHECK: sbc.w r1, r8, r9, lsr #32 @ encoding: [0x68,0xeb,0x19,0x01] +@ CHECK: sbc.w r2, r7, pc, lsr #16 @ encoding: [0x67,0xeb,0x1f,0x42] +@ CHECK: sbc.w r3, r6, r10 @ encoding: [0x66,0xeb,0x0a,0x03] +@ CHECK: sbc.w r4, r5, lr, lsl #16 @ encoding: [0x65,0xeb,0x0e,0x44] +@ CHECK: sbc.w r5, r4, r11, asr #32 @ encoding: [0x64,0xeb,0x2b,0x05] +@ CHECK: sbc.w r6, r3, sp, asr #16 @ encoding: [0x63,0xeb,0x2d,0x46] +@ CHECK: sbc.w r7, r2, r12, rrx @ encoding: [0x62,0xeb,0x3c,0x07] +@ CHECK: sbc.w r8, r1, r0, ror #16 @ encoding: [0x61,0xeb,0x30,0x48] + + and.w r12, lr, r0 + and.w r1, r8, r9, lsr #32 + and.w r2, r7, pc, lsr #16 + and.w r3, r6, r10, lsl #0 + and.w r4, r5, lr, lsl #16 + and.w r5, r4, r11, asr #32 + and.w r6, r3, sp, asr #16 + and.w r7, r2, r12, rrx + and.w r8, r1, r0, ror #16 + +@ CHECK: and.w r12, lr, r0 @ encoding: [0x0e,0xea,0x00,0x0c] +@ CHECK: and.w r1, r8, r9, lsr #32 @ encoding: [0x08,0xea,0x19,0x01] +@ CHECK: and.w r2, r7, pc, lsr #16 @ encoding: [0x07,0xea,0x1f,0x42] +@ CHECK: and.w r3, r6, r10 @ encoding: [0x06,0xea,0x0a,0x03] +@ CHECK: and.w r4, r5, lr, lsl #16 @ encoding: [0x05,0xea,0x0e,0x44] +@ CHECK: and.w r5, r4, r11, asr #32 @ encoding: [0x04,0xea,0x2b,0x05] +@ CHECK: and.w r6, r3, sp, asr #16 @ encoding: [0x03,0xea,0x2d,0x46] +@ CHECK: and.w r7, r2, r12, rrx @ encoding: [0x02,0xea,0x3c,0x07] +@ CHECK: and.w r8, r1, r0, ror #16 @ encoding: [0x01,0xea,0x30,0x48]