From: José Fonseca <jfonseca@vmware.com>
Date: Wed, 12 May 2010 13:08:22 +0000 (+0100)
Subject: gallium: Add new fine grained PIPE_CAP_xx for shader limits.
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=bfc702d1e7470d611600dad18e0f829d08281eed;p=android-x86%2Fexternal-mesa.git

gallium: Add new fine grained PIPE_CAP_xx for shader limits.

PIPE_CAP_GLSL and PIPE_CAP_SM3 not removed yet, as opcode support is not
yet covered.
---

diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst
index c5815f8939c..71b7aec35a5 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -101,6 +101,22 @@ The floating-point capabilities:
 * ``GUARD_BAND_LEFT``, ``GUARD_BAND_TOP``, ``GUARD_BAND_RIGHT``,
   ``GUARD_BAND_BOTTOM``: XXX
 
+Fragment shader limits:
+
+* ``PIPE_CAP_MAX_FS_INSTRUCTIONS``: The maximum number of instructions.
+* ``PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS``: The maximum number of arithmetic instructions.
+* ``PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS``: The maximum number of texture instructions.
+* ``PIPE_CAP_MAX_FS_TEX_INDIRECTIONS``: The maximum number of texture indirections.
+* ``PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH``: The maximum nested control flow depth.
+* ``PIPE_CAP_MAX_FS_INPUTS``: The maximum number of input registers.
+* ``PIPE_CAP_MAX_FS_CONSTS``: The maximum number of constants.
+* ``PIPE_CAP_MAX_FS_TEMPS``: The maximum number of temporary registers.
+* ``PIPE_CAP_MAX_FS_ADDRS``: The maximum number of address registers.
+* ``PIPE_CAP_MAX_FS_PREDS``: The maximum number of predicate registers.
+
+Vertex shader limits:
+
+* ``PIPE_CAP_MAX_VS_*``: Identical to ``PIPE_CAP_MAX_FS_*``.
 
 
 .. _pipe_bind:
diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h
index 7e43edcff8c..2d363dd47b6 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -457,6 +457,30 @@ enum pipe_cap {
    PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT,
    PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER,
    PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER,
+
+   /*
+    * Shader limits.
+    */
+   PIPE_CAP_MAX_FS_INSTRUCTIONS,
+   PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS,
+   PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS,
+   PIPE_CAP_MAX_FS_TEX_INDIRECTIONS,
+   PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH,
+   PIPE_CAP_MAX_FS_INPUTS,
+   PIPE_CAP_MAX_FS_CONSTS,
+   PIPE_CAP_MAX_FS_TEMPS,
+   PIPE_CAP_MAX_FS_ADDRS,
+   PIPE_CAP_MAX_FS_PREDS,
+   PIPE_CAP_MAX_VS_INSTRUCTIONS,
+   PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS,
+   PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS,
+   PIPE_CAP_MAX_VS_TEX_INDIRECTIONS,
+   PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH,
+   PIPE_CAP_MAX_VS_INPUTS,
+   PIPE_CAP_MAX_VS_CONSTS,
+   PIPE_CAP_MAX_VS_TEMPS,
+   PIPE_CAP_MAX_VS_ADDRS,
+   PIPE_CAP_MAX_VS_PREDS
 };