From: Bjorn Helgaas Date: Mon, 13 Nov 2017 21:05:50 +0000 (-0600) Subject: PCI/ASPM: Use correct capability pointer to program LTR_L1.2_THRESHOLD X-Git-Tag: android-x86-8.1-r1~2246^2~23^2~2 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=c00054f540bf81e592e1fee709b0bdbf20f478b5;p=android-x86%2Fkernel.git PCI/ASPM: Use correct capability pointer to program LTR_L1.2_THRESHOLD Previously we programmed the LTR_L1.2_THRESHOLD in the parent (upstream) device using the capability pointer of the *child* (downstream) device, which corrupted some random word of the parent's config space. Use the parent's L1 SS capability pointer to program its LTR_L1.2_THRESHOLD. Fixes: aeda9adebab8 ("PCI/ASPM: Configure L1 substate settings") Signed-off-by: Bjorn Helgaas Reviewed-by: Vidya Sagar CC: stable@vger.kernel.org # v4.11+ CC: Rajat Jain --- diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 46c59afb8355..a378dd9d2473 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -657,7 +657,7 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) 0xFF00, link->l1ss.ctl1); /* Program LTR L1.2 threshold in both ports */ - pci_clear_and_set_dword(parent, dw_cap_ptr + PCI_L1SS_CTL1, + pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, 0xE3FF0000, link->l1ss.ctl1); pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, 0xE3FF0000, link->l1ss.ctl1);