From: Bin Meng Date: Thu, 21 Apr 2022 00:33:23 +0000 (+0800) Subject: target/riscv: cpu: Enable native debug feature X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=c9711bd778bd94cef0460cf76fd8b4f64b9ad657;p=qmiga%2Fqemu.git target/riscv: cpu: Enable native debug feature Turn on native debug feature by default for all CPUs. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20220421003324.1134983-6-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 85656cdcc3..0c774056c5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -803,7 +803,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), - DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false), + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),