From: H.J. Lu Date: Thu, 20 Sep 2007 17:38:37 +0000 (+0000) Subject: gas/ X-Git-Tag: cgen-snapshot-20071001~86 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=cb7b6eb36391061508eeda94ce30c4018ce585f9;p=pf3gnuchains%2Fpf3gnuchains4x.git gas/ 2007-09-20 H.J. Lu PR 658 * config/tc-i386.c (SCALE1_WHEN_NO_INDEX): Removed. (set_allow_index_reg): New. (allow_index_reg): Likewise. (md_pseudo_table): Add "allow_index_reg" and "disallow_index_reg". (build_modrm_byte): Set i.sib.index to NO_INDEX_REGISTER for fake index registers. (i386_scale): Updated. (i386_index_check): Support fake index registers. (parse_real_register): Return NULL on eiz/riz if fake index registers aren't allowed. gas/testsuite/ 2007-09-20 H.J. Lu PR 658 * gas/i386/i386.exp: Run sib-intel, x86-64-sib and x86-64-sib-intel. * gas/i386/nops-1-i386-i686.d: Updated. * gas/i386/nops-1-i386.d: Likewise. * gas/i386/nops-1.d: Likewise. * gas/i386/nops-2-i386.d: Likewise. * gas/i386/nops-2-merom.d: Likewise. * gas/i386/nops-2.d: Likewise. * gas/i386/nops-3-i386.d: Likewise. * gas/i386/nops-3.d : Likewise. * gas/i386/sib.d: Likewise. * gas/i386/sib.s: Use %eiz in testcases. * gas/i386/sib-intel.d: New. * gas/i386/x86-64-sib-intel.d: Likewise. * gas/i386/x86-64-sib.d: Likewise. * gas/i386/x86-64-sib.s: Likewise. ld/testsuite/ 2007-09-20 H.J. Lu PR 658 * ld-i386/tlsbin.dd: Updated. * ld-i386/tlsld1.dd: Likewise. opcodes/ 2007-09-20 H.J. Lu PR 658 * 386-dis.c (index64): New. (index32): Likewise. (intel_index64): Likewise. (intel_index32): Likewise. (att_index64): Likewise. (att_index32): Likewise. (print_insn): Set index64 and index32. (OP_E_extended): Use index64/index32 for index register for SIB with INDEX == 4. * i386-opc.h (RegEiz): New. (RegRiz): Likewise. * i386-reg.tbl: Add eiz and riz. * i386-tbl.h: Regenerated. --- diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 1434860a28..88be05e9a9 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,22 @@ +2007-09-20 H.J. Lu + + PR 658 + * 386-dis.c (index64): New. + (index32): Likewise. + (intel_index64): Likewise. + (intel_index32): Likewise. + (att_index64): Likewise. + (att_index32): Likewise. + (print_insn): Set index64 and index32. + (OP_E_extended): Use index64/index32 for index register for + SIB with INDEX == 4. + + * i386-opc.h (RegEiz): New. + (RegRiz): Likewise. + + * i386-reg.tbl: Add eiz and riz. + * i386-tbl.h: Regenerated. + 2007-09-19 H.J. Lu * i386-dis.c (OP_E_extended): Always display scale for memory. diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 19b13d0dad..9a45e9100d 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1353,6 +1353,8 @@ static const char **names16; static const char **names8; static const char **names8rex; static const char **names_seg; +static const char *index64; +static const char *index32; static const char **index16; static const char *intel_names64[] = { @@ -1377,6 +1379,8 @@ static const char *intel_names8rex[] = { static const char *intel_names_seg[] = { "es", "cs", "ss", "ds", "fs", "gs", "?", "?", }; +static const char *intel_index64 = "riz"; +static const char *intel_index32 = "eiz"; static const char *intel_index16[] = { "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" }; @@ -1403,6 +1407,8 @@ static const char *att_names8rex[] = { static const char *att_names_seg[] = { "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", }; +static const char *att_index64 = "%riz"; +static const char *att_index32 = "%eiz"; static const char *att_index16[] = { "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" }; @@ -5001,6 +5007,8 @@ print_insn (bfd_vma pc, disassemble_info *info) names8 = intel_names8; names8rex = intel_names8rex; names_seg = intel_names_seg; + index64 = intel_index64; + index32 = intel_index32; index16 = intel_index16; open_char = '['; close_char = ']'; @@ -5015,6 +5023,8 @@ print_insn (bfd_vma pc, disassemble_info *info) names8 = att_names8; names8rex = att_names8rex; names_seg = att_names_seg; + index64 = att_index64; + index32 = att_index32; index16 = att_index16; open_char = '('; close_char = ')'; @@ -6318,9 +6328,7 @@ OP_E_extended (int bytemode, int sizeflag, int has_drex) havesib = 1; FETCH_DATA (the_info, codep + 1); index = (*codep >> 3) & 7; - if (address_mode == mode_64bit || index != 0x4) - /* When INDEX == 0x4 in 32 bit mode, SCALE is ignored. */ - scale = (*codep >> 6) & 3; + scale = (*codep >> 6) & 3; base = *codep & 7; USED_REX (REX_X); if (rex & REX_X) @@ -6391,19 +6399,26 @@ OP_E_extended (int bytemode, int sizeflag, int has_drex) ? names64[base] : names32[base]); if (havesib) { - if (haveindex) + /* ESP/RSP won't allow index. If base isn't ESP/RSP, + print index to tell base + index from base. */ + if (scale != 0 + || haveindex + || (havebase && base != ESP_REG_NUM)) { if (!intel_syntax || havebase) { *obufp++ = separator_char; *obufp = '\0'; } - oappend (address_mode == mode_64bit - && (sizeflag & AFLAG) - ? names64[index] : names32[index]); - } - if (scale != 0 || haveindex) - { + if (haveindex) + oappend (address_mode == mode_64bit + && (sizeflag & AFLAG) + ? names64[index] : names32[index]); + else + oappend (address_mode == mode_64bit + && (sizeflag & AFLAG) + ? index64 : index32); + *obufp++ = scale_char; *obufp = '\0'; sprintf (scratchbuf, "%d", 1 << scale); @@ -6413,7 +6428,7 @@ OP_E_extended (int bytemode, int sizeflag, int has_drex) if (intel_syntax && (disp || modrm.mod != 0 || (base & 7) == 5)) { - if ((bfd_signed_vma) disp >= 0) + if (!havedisp || (bfd_signed_vma) disp >= 0) { *obufp++ = '+'; *obufp = '\0'; @@ -6425,7 +6440,10 @@ OP_E_extended (int bytemode, int sizeflag, int has_drex) disp = - (bfd_signed_vma) disp; } - print_displacement (scratchbuf, disp); + if (havedisp) + print_displacement (scratchbuf, disp); + else + print_operand_value (scratchbuf, 1, disp); oappend (scratchbuf); } diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 00fbe1c3eb..0dda2a47bd 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -444,6 +444,9 @@ typedef struct #define RegRex64 0x2 /* Extended 8 bit register. */ unsigned int reg_num; #define RegRip ((unsigned int ) ~0) +/* EIZ and RIZ are fake index registers. */ +#define RegEiz (RegRip - 1) +#define RegRiz (RegEiz - 1) } reg_entry; diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl index 28debd7610..373aba7c6a 100644 --- a/opcodes/i386-reg.tbl +++ b/opcodes/i386-reg.tbl @@ -190,6 +190,10 @@ xmm15, RegXMM, RegRex, 7 // No type will make this register rejected for all purposes except // for addressing. This saves creating one extra type for RIP. rip, BaseIndex, 0, RegRip +// No type will make these registers rejected for all purposes except +// for addressing. +eiz, BaseIndex, 0, RegEiz +riz, BaseIndex, 0, RegRiz // fp regs. st(0), FloatReg|FloatAcc, 0, 0 st(1), FloatReg, 0, 1 diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 2f18422c96..fe585db4e0 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -13279,6 +13279,14 @@ const reg_entry i386_regtab[] = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, 0, RegRip }, + { "eiz", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + 0, RegEiz }, + { "riz", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + 0, RegRiz }, { "st(0)", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 } },