From: Andrew Trick <atrick@apple.com>
Date: Tue, 13 Nov 2012 02:35:06 +0000 (+0000)
Subject: misched: Don't consider artificial edges weak edges.
X-Git-Tag: android-x86-6.0-r1~179^2~1756
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=cf6b6131dd0da37903a6e3a5173ea12aa8263713;p=android-x86%2Fexternal-llvm.git

misched: Don't consider artificial edges weak edges.

For now be more conservative in case other out-of-tree schedulers rely
on the old behavior of artificial edges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167808 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index 2b6429fbeba..016722e7f41 100644
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -206,8 +206,7 @@ namespace llvm {
     /// not force ordering. Breaking a weak edge may require the scheduler to
     /// compensate, for example by inserting a copy.
     bool isWeak() const {
-      return getKind() == Order
-        && (Contents.OrdKind == Artificial || Contents.OrdKind == Cluster);
+      return getKind() == Order && Contents.OrdKind == Cluster;
     }
 
     /// isArtificial - Test if this is an Order dependence that is marked
diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index 4284c42eb26..f37fc82b2a9 100644
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -581,7 +581,7 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
   SUnit *SuccSU = SuccEdge->getSUnit();
 
-  if (SuccEdge->isArtificial()) {
+  if (SuccEdge->isWeak()) {
     --SuccSU->WeakPredsLeft;
     return;
   }
diff --git a/lib/CodeGen/ScheduleDAG.cpp b/lib/CodeGen/ScheduleDAG.cpp
index 62240366637..0c50db8d345 100644
--- a/lib/CodeGen/ScheduleDAG.cpp
+++ b/lib/CodeGen/ScheduleDAG.cpp
@@ -100,11 +100,8 @@ bool SUnit::addPred(const SDep &D, bool Required) {
     ++NumPreds;
     ++N->NumSuccs;
   }
-  // SD scheduler relies on artificial edges to enforce physreg
-  // antidependence, so it doesn't treat them as weak edges.
-  bool isWeak = D.isWeak() && N->isInstr();
   if (!N->isScheduled) {
-    if (isWeak) {
+    if (D.isWeak()) {
       ++WeakPredsLeft;
     }
     else {
@@ -113,7 +110,7 @@ bool SUnit::addPred(const SDep &D, bool Required) {
     }
   }
   if (!isScheduled) {
-    if (isWeak) {
+    if (D.isWeak()) {
       ++N->WeakSuccsLeft;
     }
     else {
@@ -160,9 +157,8 @@ void SUnit::removePred(const SDep &D) {
         --NumPreds;
         --N->NumSuccs;
       }
-      bool isWeak = D.isWeak() && N->isInstr();
       if (!N->isScheduled) {
-        if (isWeak)
+        if (D.isWeak())
           --WeakPredsLeft;
         else {
           assert(NumPredsLeft > 0 && "NumPredsLeft will underflow!");
@@ -170,7 +166,7 @@ void SUnit::removePred(const SDep &D) {
         }
       }
       if (!isScheduled) {
-        if (isWeak)
+        if (D.isWeak())
           --N->WeakSuccsLeft;
         else {
           assert(N->NumSuccsLeft > 0 && "NumSuccsLeft will underflow!");