From: astoria-d <astoria-d@mail.goo.ne.jp>
Date: Thu, 2 Jan 2014 09:56:25 +0000 (+0900)
Subject: simulation result broken by the unknown reason..., restored some of the codes.
X-Git-Tag: motonesfpga-gate-0.2.0~47
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=d0462153ec59522c9aff88ef557724faac731dd3;p=motonesfpga%2Fmotonesfpga.git

simulation result broken by the unknown reason..., restored some of the codes.
---

diff --git a/tools/qt_proj_test5/vga.vhd b/tools/qt_proj_test5/vga.vhd
index e13451b..c08beb6 100644
--- a/tools/qt_proj_test5/vga.vhd
+++ b/tools/qt_proj_test5/vga.vhd
@@ -283,7 +283,6 @@ begin
         end if;
     end process;
 
-    --sw_write is mealy machine. (the state is decided by both the input and current state)
     sw_state_p : process (rst_n, sdram_clk)
     begin
         if (rst_n = '0') then
@@ -345,6 +344,7 @@ begin
 --            wbs_cyc_i	<= '0';
 --            wbs_stb_i	<= '0';
 --
+--               <= sw_idle;
 --            sr_state <= sr_idle;
 --            wait_cnt := SDRAM_READ_WAIT_CNT;
 --            
@@ -399,7 +399,7 @@ begin
 --            else
 --
 --                --write to sdram
---                case sw_state is
+--                case   is
 --                when sw_idle =>
 --                    --pop data from fifo first.
 ----                    sdram_addr_inc_n <= '1';
@@ -408,13 +408,20 @@ begin
 --                    
 --                    if (f_cnt = "00000000") then
 --                        --if fifo is empty, do nothing.
+--                        f_rd <= '0';
 --                        f_val_we_n <= '1';
 --                    else
+--                        f_rd <= '1';
+--                           <= sw_pop_fifo;
 --                        f_val_we_n <= '0';
 --                    end if;
 --                
 --                when sw_pop_fifo =>
+--                    f_rd <= '0';
 --                    f_val_we_n <= '1';
+--                       <= sw_write;
+--                    --     <= sw_idle;
+--                    
 --                
 ----                    --set fifo data to sdram.
 ----                    wbs_adr_i <= sdram_write_addr;
@@ -422,32 +429,38 @@ begin
 ----                    wbs_dat_i <= "0000" & f_val;
 --
 --                when sw_write =>
+--                    f_rd <= '0';
+--                       <= sw_write_ack;
 --
 ----                    wbs_cyc_i <= '1';
 ----                    wbs_stb_i <= '1';
 ----                    wbs_tga_i <= f_cnt;
 --                    
 --                when sw_write_ack =>
+--                    f_rd <= '0';
 --                    sdram_addr_inc_n <= '0';
 --                    if (f_emp = '0') then
---                        sw_state <= sw_write_burst;
+--                           <= sw_write_burst;
 --                    else
 --                        ---write finished.
---                        sw_state <= sw_idle;
+--                           <= sw_idle;
 --                    end if;
 --
 --                when sw_write_burst =>
+--                    f_rd <= '0';
 --                    wbs_adr_i <= sdram_write_addr;
 --                    --wbs_adr_i <= (others => '1');
 --                    wbs_dat_i <= "0000" & f_val;
 --                    if (f_emp = '0') then
---                        sw_state <= sw_write_burst;
+--                           <= sw_write_burst;
 --                    else
 --                        ---write finished.
---                        sw_state <= sw_idle;
+--                           <= sw_idle;
 --                    end if;
 --                
 --                when others =>
+--                    f_rd <= '0';
+--                       <= sw_idle;
 --                end case;
 --
 --                --for sdram read...