From: Simon Pilgrim Date: Mon, 2 May 2016 14:58:22 +0000 (+0000) Subject: [X86][SSE] Dropped X86ISD::FGETSIGNx86 and use MOVMSK instead for FGETSIGN lowering X-Git-Tag: android-x86-7.1-r4~34195 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=d0941fb7bb91bb698f4db0c2c02f2354e847b830;p=android-x86%2Fexternal-llvm.git [X86][SSE] Dropped X86ISD::FGETSIGNx86 and use MOVMSK instead for FGETSIGN lowering movmsk.ll tests are unchanged. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268237 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 82d2218f0b1..7b9c3de0d44 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -508,7 +508,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::FSINCOS, VT, Expand); } - // Lower this to FGETSIGNx86 plus an AND. + // Lower this to MOVMSK plus an AND. setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); @@ -14222,10 +14222,17 @@ static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) { SDLoc dl(Op); MVT VT = Op.getSimpleValueType(); - // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). - SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, - DAG.getConstant(1, dl, VT)); - return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT)); + MVT OpVT = N0.getSimpleValueType(); + assert((OpVT == MVT::f32 || OpVT == MVT::f64) && + "Unexpected type for FGETSIGN"); + + // Lower ISD::FGETSIGN to (AND (X86ISD::MOVMSK ...) 1). + MVT VecVT = (OpVT == MVT::f32 ? MVT::v4f32 : MVT::v2f64); + SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, N0); + Res = DAG.getNode(X86ISD::MOVMSK, dl, MVT::i32, Res); + Res = DAG.getZExtOrTrunc(Res, dl, VT); + Res = DAG.getNode(ISD::AND, dl, VT, Res, DAG.getConstant(1, dl, VT)); + return Res; } // Check whether an OR'd tree is PTEST-able. @@ -21616,7 +21623,6 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { case X86ISD::SETCC: return "X86ISD::SETCC"; case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; case X86ISD::FSETCC: return "X86ISD::FSETCC"; - case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86"; case X86ISD::CMOV: return "X86ISD::CMOV"; case X86ISD::BRCOND: return "X86ISD::BRCOND"; case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index cbe7d5732e2..3a99d4d089f 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -106,10 +106,6 @@ namespace llvm { /// 0s or 1s. Generally DTRT for C/C++ with NaNs. FSETCC, - /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values, - /// result in an integer GPR. Needs masking for scalar result. - FGETSIGNx86, - /// X86 conditional moves. Operand 0 and operand 1 are the two values /// to select from. Operand 2 is the condition code, and operand 3 is the /// flag operand produced by a CMP or TEST instruction. It also writes a diff --git a/lib/Target/X86/X86InstrFragmentsSIMD.td b/lib/Target/X86/X86InstrFragmentsSIMD.td index 2c75ad3fbf4..f3092f51a14 100644 --- a/lib/Target/X86/X86InstrFragmentsSIMD.td +++ b/lib/Target/X86/X86InstrFragmentsSIMD.td @@ -62,7 +62,6 @@ def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>; def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>; def X86frsqrt14s: SDNode<"X86ISD::FRSQRT", SDTFPBinOp>; def X86frcp14s : SDNode<"X86ISD::FRCP", SDTFPBinOp>; -def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>; def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>; def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>; def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>; diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 23c66c99f5e..21852a2d90d 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -2774,17 +2774,6 @@ let Predicates = [HasAVX] in { SSEPackedSingle>, PS, VEX, VEX_L; defm VMOVMSKPDY : sse12_extr_sign_mask, PD, VEX, VEX_L; - - def : Pat<(i32 (X86fgetsign FR32:$src)), - (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>; - def : Pat<(i64 (X86fgetsign FR32:$src)), - (SUBREG_TO_REG (i64 0), - (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>; - def : Pat<(i32 (X86fgetsign FR64:$src)), - (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>; - def : Pat<(i64 (X86fgetsign FR64:$src)), - (SUBREG_TO_REG (i64 0), - (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>; } defm MOVMSKPS : sse12_extr_sign_mask, PD; -def : Pat<(i32 (X86fgetsign FR32:$src)), - (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>, - Requires<[UseSSE1]>; -def : Pat<(i64 (X86fgetsign FR32:$src)), - (SUBREG_TO_REG (i64 0), - (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>, - Requires<[UseSSE1]>; -def : Pat<(i32 (X86fgetsign FR64:$src)), - (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>, - Requires<[UseSSE2]>; -def : Pat<(i64 (X86fgetsign FR64:$src)), - (SUBREG_TO_REG (i64 0), - (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>, - Requires<[UseSSE2]>; - //===---------------------------------------------------------------------===// // SSE2 - Packed Integer Logical Instructions //===---------------------------------------------------------------------===//