From: Chao-ying Fu Date: Tue, 7 Apr 2015 23:03:04 +0000 (-0700) Subject: x86_64: Fix the rex prefix for movzxb, movsxb, movb X-Git-Tag: android-x86-7.1-r1~889^2~1581^2 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=d23840d3ed900c6072d71e6599b3568b68de6b7c;p=android-x86%2Fart.git x86_64: Fix the rex prefix for movzxb, movsxb, movb This patch sets the rex prefix for the source byte register of movzxb, movsxb, and movb that has the destination memory operand, when the register is SPL, BPL, SIL, DIL. This patch adds tests for movzxb and movsxb via Repeatrb(), and adds the tertiary and quaternary register views for word and byte registers on x86_64. TODO: Support tests with memory operands. Change-Id: I0c5c727f3dd4a75af039b87f7e57d0741e689038 Signed-off-by: Chao-ying Fu --- diff --git a/compiler/utils/assembler_test.h b/compiler/utils/assembler_test.h index b13edb68b..3fe1a31d7 100644 --- a/compiler/utils/assembler_test.h +++ b/compiler/utils/assembler_test.h @@ -44,7 +44,9 @@ static std::string tmpnam_; enum class RegisterView { // private kUsePrimaryName, - kUseSecondaryName + kUseSecondaryName, + kUseTertiaryName, + kUseQuaternaryName, }; template @@ -97,6 +99,15 @@ class AssemblerTest : public testing::Test { fmt); } + std::string Repeatrb(void (Ass::*f)(Reg, Reg), std::string fmt) { + return RepeatTemplatedRegisters(f, + GetRegisters(), + GetRegisters(), + &AssemblerTest::GetRegName, + &AssemblerTest::GetRegName, + fmt); + } + std::string RepeatRr(void (Ass::*f)(Reg, Reg), std::string fmt) { return RepeatTemplatedRegisters(f, GetRegisters(), @@ -240,6 +251,18 @@ class AssemblerTest : public testing::Test { UNREACHABLE(); } + // Tertiary register names are the tertiary view on registers, e.g., 16b on 64b systems. + virtual std::string GetTertiaryRegisterName(const Reg& reg ATTRIBUTE_UNUSED) { + UNIMPLEMENTED(FATAL) << "Architecture does not support tertiary registers"; + UNREACHABLE(); + } + + // Quaternary register names are the quaternary view on registers, e.g., 8b on 64b systems. + virtual std::string GetQuaternaryRegisterName(const Reg& reg ATTRIBUTE_UNUSED) { + UNIMPLEMENTED(FATAL) << "Architecture does not support quaternary registers"; + UNREACHABLE(); + } + std::string GetRegisterName(const Reg& reg) { return GetRegName(reg); } @@ -520,6 +543,14 @@ class AssemblerTest : public testing::Test { case RegisterView::kUseSecondaryName: sreg << GetSecondaryRegisterName(reg); break; + + case RegisterView::kUseTertiaryName: + sreg << GetTertiaryRegisterName(reg); + break; + + case RegisterView::kUseQuaternaryName: + sreg << GetQuaternaryRegisterName(reg); + break; } return sreg.str(); } diff --git a/compiler/utils/x86_64/assembler_x86_64.cc b/compiler/utils/x86_64/assembler_x86_64.cc index e82d90c5c..9ad31c725 100644 --- a/compiler/utils/x86_64/assembler_x86_64.cc +++ b/compiler/utils/x86_64/assembler_x86_64.cc @@ -210,7 +210,9 @@ void X86_64Assembler::movzxb(CpuRegister dst, CpuRegister src) { void X86_64Assembler::movzxb(CpuRegister dst, const Address& src) { AssemblerBuffer::EnsureCapacity ensured(&buffer_); - EmitOptionalByteRegNormalizingRex32(dst, src); + // Byte register is only in the source register form, so we don't use + // EmitOptionalByteRegNormalizingRex32(dst, src); + EmitOptionalRex32(dst, src); EmitUint8(0x0F); EmitUint8(0xB6); EmitOperand(dst.LowBits(), src); @@ -228,7 +230,9 @@ void X86_64Assembler::movsxb(CpuRegister dst, CpuRegister src) { void X86_64Assembler::movsxb(CpuRegister dst, const Address& src) { AssemblerBuffer::EnsureCapacity ensured(&buffer_); - EmitOptionalByteRegNormalizingRex32(dst, src); + // Byte register is only in the source register form, so we don't use + // EmitOptionalByteRegNormalizingRex32(dst, src); + EmitOptionalRex32(dst, src); EmitUint8(0x0F); EmitUint8(0xBE); EmitOperand(dst.LowBits(), src); @@ -2155,11 +2159,18 @@ void X86_64Assembler::EmitRex64(CpuRegister dst, const Operand& operand) { } void X86_64Assembler::EmitOptionalByteRegNormalizingRex32(CpuRegister dst, CpuRegister src) { - EmitOptionalRex(true, false, dst.NeedsRex(), false, src.NeedsRex()); + // For src, SPL, BPL, SIL, DIL need the rex prefix. + bool force = src.AsRegister() > 3; + EmitOptionalRex(force, false, dst.NeedsRex(), false, src.NeedsRex()); } void X86_64Assembler::EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand) { - uint8_t rex = 0x40 | operand.rex(); // REX.0000 + uint8_t rex = operand.rex(); + // For dst, SPL, BPL, SIL, DIL need the rex prefix. + bool force = dst.AsRegister() > 3; + if (force) { + rex |= 0x40; // REX.0000 + } if (dst.NeedsRex()) { rex |= 0x44; // REX.0R00 } diff --git a/compiler/utils/x86_64/assembler_x86_64_test.cc b/compiler/utils/x86_64/assembler_x86_64_test.cc index 4402dfcb3..b90c14213 100644 --- a/compiler/utils/x86_64/assembler_x86_64_test.cc +++ b/compiler/utils/x86_64/assembler_x86_64_test.cc @@ -174,6 +174,40 @@ class AssemblerX86_64Test : public AssemblerTest registers_; std::map secondary_register_names_; + std::map tertiary_register_names_; + std::map quaternary_register_names_; std::vector fp_registers_; }; @@ -824,31 +870,12 @@ std::string setcc_test_fn(AssemblerX86_64Test::Base* assembler_test, "l", "ge", "le" }; std::vector registers = assembler_test->GetRegisters(); - - std::string byte_regs[16]; - byte_regs[x86_64::RAX] = "al"; - byte_regs[x86_64::RBX] = "bl"; - byte_regs[x86_64::RCX] = "cl"; - byte_regs[x86_64::RDX] = "dl"; - byte_regs[x86_64::RBP] = "bpl"; - byte_regs[x86_64::RSP] = "spl"; - byte_regs[x86_64::RSI] = "sil"; - byte_regs[x86_64::RDI] = "dil"; - byte_regs[x86_64::R8] = "r8b"; - byte_regs[x86_64::R9] = "r9b"; - byte_regs[x86_64::R10] = "r10b"; - byte_regs[x86_64::R11] = "r11b"; - byte_regs[x86_64::R12] = "r12b"; - byte_regs[x86_64::R13] = "r13b"; - byte_regs[x86_64::R14] = "r14b"; - byte_regs[x86_64::R15] = "r15b"; - std::ostringstream str; for (auto reg : registers) { for (size_t i = 0; i < 15; ++i) { assembler->setcc(static_cast(i), *reg); - str << "set" << suffixes[i] << " %" << byte_regs[reg->AsRegister()] << "\n"; + str << "set" << suffixes[i] << " %" << assembler_test->GetQuaternaryRegisterName(*reg) << "\n"; } } @@ -979,4 +1006,12 @@ TEST_F(AssemblerX86_64Test, DecreaseFrame) { DriverFn(&decreaseframe_test_fn, "DecreaseFrame"); } +TEST_F(AssemblerX86_64Test, MovzxbRegs) { + DriverStr(Repeatrb(&x86_64::X86_64Assembler::movzxb, "movzbl %{reg2}, %{reg1}"), "movzxb"); +} + +TEST_F(AssemblerX86_64Test, MovsxbRegs) { + DriverStr(Repeatrb(&x86_64::X86_64Assembler::movsxb, "movsbl %{reg2}, %{reg1}"), "movsxb"); +} + } // namespace art