From: Alex Bradbury <asb@lowrisc.org>
Date: Thu, 15 Nov 2018 14:46:11 +0000 (+0000)
Subject: [RISCV] Mark FREM as Expand
X-Git-Tag: android-x86-9.0-r1~10584
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=d566da724ad9c7b4f391ee61e51714e5d39cacad;p=android-x86%2Fexternal-llvm.git

[RISCV] Mark FREM as Expand

Mark the FREM SelectionDAG node as Expand, which is necessary in order to
support the frem IR instruction on RISC-V. This is expanded into a library
call. Adds the corresponding test. Previously, this would have triggered an
assertion at instruction selection time.

Differential Revision: https://reviews.llvm.org/D54159
Patch by Luís Marques.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346958 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/RISCV/RISCVISelLowering.cpp b/lib/Target/RISCV/RISCVISelLowering.cpp
index 85758c0cdf8..56900a6dcef 100644
--- a/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -114,7 +114,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   // TODO: add proper support for the various FMA variants
   // (FMADD.S, FMSUB.S, FNMSUB.S, FNMADD.S).
   ISD::NodeType FPOpToExtend[] = {
-      ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FMA};
+      ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FMA, ISD::FREM};
 
   if (Subtarget.hasStdExtF()) {
     setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
diff --git a/test/CodeGen/RISCV/double-frem.ll b/test/CodeGen/RISCV/double-frem.ll
new file mode 100644
index 00000000000..07f84ac11ce
--- /dev/null
+++ b/test/CodeGen/RISCV/double-frem.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32ID %s
+
+define double @frem_f64(double %a, double %b) nounwind {
+; RV32ID-LABEL: frem_f64:
+; RV32ID:       # %bb.0:
+; RV32ID-NEXT:    addi sp, sp, -16
+; RV32ID-NEXT:    sw ra, 12(sp)
+; RV32ID-NEXT:    call fmod
+; RV32ID-NEXT:    lw ra, 12(sp)
+; RV32ID-NEXT:    addi sp, sp, 16
+; RV32ID-NEXT:    ret
+  %1 = frem double %a, %b
+  ret double %1
+}
diff --git a/test/CodeGen/RISCV/float-frem.ll b/test/CodeGen/RISCV/float-frem.ll
new file mode 100644
index 00000000000..95042c5fde6
--- /dev/null
+++ b/test/CodeGen/RISCV/float-frem.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32IF %s
+
+define float @frem_f32(float %a, float %b) nounwind {
+; RV32IF-LABEL: frem_f32:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    call fmodf
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+  %1 = frem float %a, %b
+  ret float %1
+}