From: yujiro_kaeko <zyangalianhamster01@gmail.com>
Date: Thu, 30 Jun 2011 12:04:47 +0000 (+0900)
Subject: Merge remote branch 'origin/master'
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=d8536851295fe5fe995b29c95b90659274700d80;hp=f62359426962e40743214a2065f18898cac23a21;p=oca1%2Ftest.git

Merge remote branch 'origin/master'
---

diff --git a/VGADisplay/src/memo b/VGADisplay/src/memo
index e16ba19..642d458 100644
--- a/VGADisplay/src/memo
+++ b/VGADisplay/src/memo
@@ -21,5 +21,5 @@ output q[8];
 
 VHDL VerilogHDL‚̃vƒ‰ƒOƒCƒ“‚ð‚¢‚ê‚Ä‚¨‚­B
 
-1. ‰¼‘zƒƒ‚ƒŠ‚Æexp_ctrl‚ðƒeƒXƒg
+1.‰¼‘zƒƒ‚ƒŠ‚Æexp_ctrl‚ðƒeƒXƒg
 ‚QDƒƒ‚ƒŠŽÀ‹@ƒeƒXƒg
\ No newline at end of file
diff --git a/VGADisplay/src/top.nsl b/VGADisplay/src/top.nsl
deleted file mode 100644
index 714bc47..0000000
--- a/VGADisplay/src/top.nsl
+++ /dev/null
@@ -1,64 +0,0 @@
-#define SIM
-
-#include "vga_generate.nsl"
-#include "exp_ctrl.nsl"
-
-#define ONE_SEC 25'd50000000
-
-declare vga_top {
-	output v_sync_o ;
-	output h_sync_o ;
-	output vga_red_o[4] ;
-	output vga_green_o[4] ;
-	output vga_blue_o[4] ;
-}
-module vga_top {
-	integer i ;
-
-	reg cnt = 0 ;
-	reg reset[3] = 0b111 ;
-	reg line_cnt[7] = 0 ;
-	reg vram_adrs_cnt[14] = 0 ;
-	reg rSec_cnt[25] = 0 ;
-	
-	mem line_buff1[80][8] ;
-	mem line_buff2[80][8] ;
-
-	func_self vga_sys_init ;
-
-	vga_generate U_VGA ;
-	exp_ctrl U_EXP ;
-	
-	U_VGA.pix32_data_i = 32'd0 ;
-	
-	v_sync_o	= U_VGA.v_sync_o ;
-	h_sync_o	= U_VGA.h_sync_o ;
-	vga_red_o	= U_VGA.vga_red_o ;
-	vga_green_o = U_VGA.vga_green_o ;
-	vga_blue_o	= U_VGA.vga_blue_o ;
-
-	{
-		cnt := ~cnt ;
-
-		reset := { reset[1:0], 0b0 } ;
-
-		U_VGA.p_reset = reset[2] ;
-		U_VGA.m_clock = cnt ;
-	
-		any {
-			rSec_cnt == ONE_SEC : {
-				
-				rSec_cnt := 0 ;
-			}
-			else : {
-				rSec_cnt++ ;
-			}
-		}
-	}
-	
-	func vga_sys_init seq {
-//		for(line_cnt:=0;line_cnt<80;line_cnt++) {
-//			line_buff1[line_cnt] := 
-//		}
-	}
-}
\ No newline at end of file
diff --git a/VGADisplay/src/vga_generate.nsl b/VGADisplay/src/vga_generate.nsl
index 9d5d0fc..5af645d 100644
--- a/VGADisplay/src/vga_generate.nsl
+++ b/VGADisplay/src/vga_generate.nsl
@@ -160,8 +160,8 @@ module vga_generate {
 
 		if (hdata_flg & vdata_flg) {
 			red = 4'h0;
-			blue = 4'h0;
-			green = 4'hF;
+			blue = 4'hF;
+			green = 4'h0;
 
 /*
 			any {
@@ -175,8 +175,8 @@ module vga_generate {
 					blue	= 4'h0 ;
 					green	= 4'h0 ;
 				}
-*/
 			}
+*/
 		} else {
 			red		= 4'h0 ;
 			blue	= 4'h0 ;
diff --git a/VGADisplay/src/vga_top.nsl b/VGADisplay/src/vga_top.nsl
new file mode 100644
index 0000000..f2622be
--- /dev/null
+++ b/VGADisplay/src/vga_top.nsl
@@ -0,0 +1,105 @@
+#define SIM
+
+#include "vga_generate.nsl"
+#include "exp_ctrl.nsh"
+
+// #define ONE_SEC 25'd50000000
+#define ONE_SEC 25'd100
+
+
+declare vga_top {
+	output v_sync_o ;
+	output h_sync_o ;
+	output vga_red_o[4] ;
+	output vga_green_o[4] ;
+	output vga_blue_o[4] ;
+	
+	output oLED[8] ;
+}
+module vga_top {
+	integer i ;
+
+	reg cnt = 0 ;
+	reg reset[3] = 0b111 ;
+	reg line_cnt[15] = 0 ;
+	reg line_cnt2[14] = 0 ;
+	reg vram_adrs_cnt[14] = 0 ;
+	reg rSec_cnt[25] = 0 ;
+	reg rInit_flag = 0 ;
+	reg rLED[8] = 0 ;
+	reg test_LED = 0 ;
+	
+	mem line_buff1[80][8] ;
+	mem line_buff2[80][8] ;
+
+	func_self vga_sys_init ;
+
+	vga_generate U_VGA ;
+	exp_ctrl U_EXP ;
+	
+	v_sync_o	= U_VGA.v_sync_o ;
+	h_sync_o	= U_VGA.h_sync_o ;
+	vga_red_o	= U_VGA.vga_red_o ;
+	vga_green_o = U_VGA.vga_green_o ;
+	vga_blue_o	= U_VGA.vga_blue_o ;
+
+	if( U_VGA.req_32dot ) {
+		U_VGA.ack_req_32dot( 32'hFFFFFFFF ) ;
+	}
+
+	{
+		cnt := ~cnt ;
+		oLED = rLED ;
+
+		reset := { reset[1:0], 0b0 } ;
+		if( reset == 0b100 ) vga_sys_init() ;
+
+		U_VGA.p_reset = reset[2] ;
+		U_VGA.m_clock = cnt ;
+		
+		if( U_EXP.foRd_ack ) {
+			rLED := {
+//				U_EXP.oRdata[14],
+				U_EXP.oRdata[12],
+				U_EXP.oRdata[10],
+				U_EXP.oRdata[8],
+				U_EXP.oRdata[6],
+				U_EXP.oRdata[4],
+				U_EXP.oRdata[2],
+				U_EXP.oRdata[0],
+				test_LED
+			} ;
+		}
+	
+		if( rInit_flag ) {
+			any {
+				rSec_cnt == ONE_SEC : {
+					U_EXP.fiRd_req( line_cnt2 ) ;
+					rSec_cnt := 0 ;
+					test_LED := ~test_LED ;
+					any {
+						line_cnt2 == 14'd1000 : line_cnt2 := 0 ;
+						else : line_cnt2++ ;
+					}
+				}
+				else : {
+					rSec_cnt++ ;
+				}
+			}
+		} else {
+			rSec_cnt := 0 ;
+		}
+	}
+	
+	func vga_sys_init seq {
+//		for(line_cnt=0;line_cnt<80;line_cnt++) {
+//			line_buff1[line_cnt] := 
+//		}
+
+		for( line_cnt:=0; line_cnt<16384; line_cnt++ ) {
+			U_EXP.fiWr_req( line_cnt, line_cnt[7:0] ) ;
+		}
+		
+		rInit_flag := 1 ;
+	}
+}
\ No newline at end of file