From: Johnny Chen Date: Wed, 6 Apr 2011 22:14:48 +0000 (+0000) Subject: A8.6.393 X-Git-Tag: android-x86-6.0-r1~990^2~44 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=d8b4c4d74f745e6d556e96e056fe774c7cbef697;p=android-x86%2Fexternal-llvm.git A8.6.393 The ARM disassembler should reject invalid (type, align) encodings as invalid instructions. So, instead of: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- vst2.32 {d0, d2}, [r3, :256], r3 we now have: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- mc-input.txt:1:1: warning: invalid instruction encoding 0xb3 0x9 0x3 0xf4 ^ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129033 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 8d4f8d86c20..2e911c453e8 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -2497,22 +2497,22 @@ static bool DisassembleNLdSt(MCInst &MI, unsigned Opcode, uint32_t insn, // 0 represents standard alignment, i.e., unaligned data access. unsigned alignment = 0; - if (Name.find("LN") != std::string::npos) { - // To one lane instructions. - // See, for example, 8.6.317 VLD4 (single 4-element structure to one lane). + unsigned elem = 0; // legal values: {1, 2, 3, 4} + if (Name.startswith("VST1") || Name.startswith("VLD1")) + elem = 1; - unsigned elem = 0; // legal values: {1, 2, 3, 4} - if (Name.startswith("VST1") || Name.startswith("VLD1")) - elem = 1; + if (Name.startswith("VST2") || Name.startswith("VLD2")) + elem = 2; - if (Name.startswith("VST2") || Name.startswith("VLD2")) - elem = 2; + if (Name.startswith("VST3") || Name.startswith("VLD3")) + elem = 3; - if (Name.startswith("VST3") || Name.startswith("VLD3")) - elem = 3; + if (Name.startswith("VST4") || Name.startswith("VLD4")) + elem = 4; - if (Name.startswith("VST4") || Name.startswith("VLD4")) - elem = 4; + if (Name.find("LN") != std::string::npos) { + // To one lane instructions. + // See, for example, 8.6.317 VLD4 (single 4-element structure to one lane). // Utility function takes number of elements, size, and index_align. if (!Align4OneLaneInst(elem, @@ -2533,7 +2533,8 @@ static bool DisassembleNLdSt(MCInst &MI, unsigned Opcode, uint32_t insn, // See, for example, A8.6.316 VLD4 (multiple 4-element structures). // Inst{5-4} encodes alignment. - switch (slice(insn, 5, 4)) { + unsigned align = slice(insn, 5, 4); + switch (align) { default: break; case 1: @@ -2544,22 +2545,42 @@ static bool DisassembleNLdSt(MCInst &MI, unsigned Opcode, uint32_t insn, alignment = 256; break; } - // n == 2 && type == 0b1001 -> DblSpaced = true - if (Name.startswith("VST2") || Name.startswith("VLD2")) - DblSpaced = slice(insn, 11, 8) == 9; - - // n == 3 && type == 0b0101 -> DblSpaced = true - if (Name.startswith("VST3") || Name.startswith("VLD3")) { + unsigned type = slice(insn, 11, 8); + // Reject UNDEFINED instructions based on type and align. + // Plus set DblSpaced flag where appropriate. + switch (elem) { + default: + break; + case 1: + // n == 1 + // A8.6.307 & A8.6.391 + if ((type == 7 && slice(align, 1, 1) == 1) || + (type == 10 && align == 3) || + (type == 6 && slice(align, 1, 1) == 1)) + return false; + break; + case 2: + // n == 2 && type == 0b1001 -> DblSpaced = true + // A8.6.310 & A8.6.393 + if ((type == 8 || type == 9) && align == 3) + return false; + DblSpaced = (type == 9); + break; + case 3: + // n == 3 && type == 0b0101 -> DblSpaced = true // A8.6.313 & A8.6.395 - if (slice(insn, 7, 6) == 3 && slice(insn, 5, 5) == 1) + if (slice(insn, 7, 6) == 3 || slice(align, 1, 1) == 1) return false; - - DblSpaced = slice(insn, 11, 8) == 5; + DblSpaced = (type == 5); + break; + case 4: + // n == 4 && type == 0b0001 -> DblSpaced = true + // A8.6.316 & A8.6.397 + if (slice(insn, 7, 6) == 3) + return false; + DblSpaced = (type == 1); + break; } - - // n == 4 && type == 0b0001 -> DblSpaced = true - if (Name.startswith("VST4") || Name.startswith("VLD4")) - DblSpaced = slice(insn, 11, 8) == 1; } return DisassembleNLdSt0(MI, Opcode, insn, NumOps, NumOpsAdded, slice(insn, 21, 21) == 0, DblSpaced, alignment/8, B); diff --git a/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt new file mode 100644 index 00000000000..506250c3bc2 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.393 VST2 (multiple 2-element structures) +# type == '1001' and align == '11' ==> UNDEFINED +0xb3 0x9 0x3 0xf4