From: Matt Beaumont-Gay <matthewbg@google.com>
Date: Tue, 22 Mar 2011 00:37:28 +0000 (+0000)
Subject: Avoid -Wunused-variable in -asserts builds
X-Git-Tag: android-x86-6.0-r1~990^2~474
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=ddb657c63dd0865c13cf677484b59fc5f9758d1b;p=android-x86%2Fexternal-llvm.git

Avoid -Wunused-variable in -asserts builds

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128048 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
index da4faf4971a..b9cafeb831b 100644
--- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
+++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
@@ -607,11 +607,6 @@ static bool DisassembleThumb1LdSt(unsigned opA, MCInst &MI, unsigned Opcode,
   const TargetOperandInfo *OpInfo = TID.OpInfo;
   unsigned &OpIdx = NumOpsAdded;
 
-  // Table A6-5 16-bit Thumb Load/store instructions
-  // opA = 0b0101 for STR/LDR (register) and friends.
-  // Otherwise, we have STR/LDR (immediate) and friends.
-  bool Imm5 = (opA != 5);
-
   assert(NumOps >= 2
          && OpInfo[0].RegClass == ARM::tGPRRegClassID
          && OpInfo[1].RegClass == ARM::tGPRRegClassID
@@ -632,7 +627,10 @@ static bool DisassembleThumb1LdSt(unsigned opA, MCInst &MI, unsigned Opcode,
 
   if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() &&
       !OpInfo[OpIdx].isOptionalDef()) {
-    assert(Imm5 && "Immediate operand expected for this opcode");
+    // Table A6-5 16-bit Thumb Load/store instructions
+    // opA = 0b0101 for STR/LDR (register) and friends.
+    // Otherwise, we have STR/LDR (immediate) and friends.
+    assert(opA != 5 && "Immediate operand expected for this opcode");
     MI.addOperand(MCOperand::CreateImm(getT1Imm5(insn)));
     ++OpIdx;
   } else {