From: Simon Pilgrim Date: Sat, 9 Dec 2017 23:42:56 +0000 (+0000) Subject: [InstCombine] Fix SimplifyDemandedUseBits SHL handling (PR35515) X-Git-Tag: android-x86-7.1-r4~7506 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=e3aae88e027871c05d1cf64e57aece7791ccb024;p=android-x86%2Fexternal-llvm.git [InstCombine] Fix SimplifyDemandedUseBits SHL handling (PR35515) Don't assume that the pattern matched SRL can be cast to an Instruction (might be ConstExpr etc.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320270 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp index 7d5d28f6fc4..a2e757cb427 100644 --- a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -435,12 +435,11 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask, const APInt *SA; if (match(I->getOperand(1), m_APInt(SA))) { const APInt *ShrAmt; - if (match(I->getOperand(0), m_Shr(m_Value(), m_APInt(ShrAmt)))) { - Instruction *Shr = cast(I->getOperand(0)); - if (Value *R = simplifyShrShlDemandedBits( - Shr, *ShrAmt, I, *SA, DemandedMask, Known)) - return R; - } + if (match(I->getOperand(0), m_Shr(m_Value(), m_APInt(ShrAmt)))) + if (Instruction *Shr = dyn_cast(I->getOperand(0))) + if (Value *R = simplifyShrShlDemandedBits(Shr, *ShrAmt, I, *SA, + DemandedMask, Known)) + return R; uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt)); diff --git a/test/Transforms/InstCombine/pr35515.ll b/test/Transforms/InstCombine/pr35515.ll new file mode 100644 index 00000000000..1ad9b2fccd9 --- /dev/null +++ b/test/Transforms/InstCombine/pr35515.ll @@ -0,0 +1,20 @@ +; RUN: opt -S -instcombine < %s | FileCheck %s + +@g_40 = external global i8, align 2 +@g_461 = external global [6 x i8], align 2 +@g_49 = external local_unnamed_addr global { i8, i8, i8, i8, i8 }, align 2 + +; CHECK-LABEL: @func_24( +define fastcc void @func_24() { +entry: + %bf.load81 = load i40, i40* bitcast ({ i8, i8, i8, i8, i8 }* @g_49 to i40*), align 2 + %bf.clear = and i40 %bf.load81, -274869518337 + %bf.set = or i40 %bf.clear, shl (i40 zext (i1 icmp sgt (i32 zext (i1 icmp eq (i8* getelementptr inbounds ([6 x i8], [6 x i8]* @g_461, i64 0, i64 2), i8* @g_40) to i32), i32 0) to i40), i40 23) + %tmp = lshr i40 %bf.set, 23 + %tmp1 = trunc i40 %tmp to i32 + %tmp2 = and i32 1, %tmp1 + %tmp3 = shl nuw nsw i32 %tmp2, 23 + %bf.shl154 = zext i32 %tmp3 to i40 + %bf.set156 = or i40 %bf.clear, %bf.shl154 + unreachable +}