From: Marek Olšák Date: Fri, 20 Jan 2017 00:13:39 +0000 (+0100) Subject: radeonsi: always set the TCL1_ACTION_ENA when invalidating L2 X-Git-Tag: android-x86-6.0-r3~259 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=e405d0d3c653dc00049e2c713dbc158014055529;p=android-x86%2Fexternal-mesa.git radeonsi: always set the TCL1_ACTION_ENA when invalidating L2 Some CIK-VI docs say this is the default behavior on SI. That doesn't answer whether it's also the default behavior on CIK-VI. Cc: 17.0 13.0 Reviewed-by: Nicolai Hähnle (cherry picked from commit 573bf0940a08e18a511e338de478f30fd95a1590) --- diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 837c0250eda..d296874a23b 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -850,11 +850,12 @@ void si_emit_cache_flush(struct si_context *sctx) if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2 || (rctx->chip_class <= CIK && (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) { - /* Invalidate L1 & L2. (L1 is always invalidated) + /* Invalidate L1 & L2. (L1 is always invalidated on SI) * WB must be set on VI+ when TC_ACTION is set. */ si_emit_surface_sync(rctx, cp_coher_cntl | S_0085F0_TC_ACTION_ENA(1) | + S_0085F0_TCL1_ACTION_ENA(1) | S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class >= VI)); cp_coher_cntl = 0; sctx->b.num_L2_invalidates++;